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Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
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@ -147,6 +147,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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if (!TM.Options.NoNaNsFPMath) {
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setOperationAction(ISD::FABS, MVT::f32, Custom);
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setOperationAction(ISD::FABS, MVT::f64, Custom);
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}
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if (HasMips64) {
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if (HasMips64) {
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
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@ -734,6 +739,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
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case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
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case ISD::FABS: return LowerFABS(Op, DAG);
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case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
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case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
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case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
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@ -1857,6 +1863,63 @@ MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
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return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
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}
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}
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static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
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SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
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DebugLoc DL = Op.getDebugLoc();
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// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
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// to i32.
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SDValue X = (Op.getValueType() == MVT::f32) ?
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DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
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DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
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Const1);
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// Clear MSB.
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if (HasR2)
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Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
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DAG.getRegister(Mips::ZERO, MVT::i32),
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DAG.getConstant(31, MVT::i32), Const1, X);
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else {
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SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
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Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
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}
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if (Op.getValueType() == MVT::f32)
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return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
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SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
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Op.getOperand(0), DAG.getConstant(0, MVT::i32));
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return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
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}
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static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
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SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
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DebugLoc DL = Op.getDebugLoc();
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// Bitcast to integer node.
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SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
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// Clear MSB.
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if (HasR2)
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Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
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DAG.getRegister(Mips::ZERO_64, MVT::i64),
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DAG.getConstant(63, MVT::i32), Const1, X);
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else {
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SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
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Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
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}
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return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
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}
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SDValue
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MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
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if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
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return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
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return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
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}
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SDValue MipsTargetLowering::
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SDValue MipsTargetLowering::
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LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
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LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
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// check the depth
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// check the depth
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@ -131,6 +131,7 @@ namespace llvm {
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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@ -190,6 +190,7 @@ let Predicates = [IsFP64bit] in {
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def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
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def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
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}
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}
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let Predicates = [NoNaNsFPMath] in
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defm FABS : FFR1P_M<0x5, "abs", fabs>;
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defm FABS : FFR1P_M<0x5, "abs", fabs>;
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defm FNEG : FFR1P_M<0x7, "neg", fneg>;
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defm FNEG : FFR1P_M<0x7, "neg", fneg>;
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defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
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defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
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52
test/CodeGen/Mips/fabs.ll
Normal file
52
test/CodeGen/Mips/fabs.ll
Normal file
@ -0,0 +1,52 @@
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; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN
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define float @foo0(float %a) nounwind readnone {
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entry:
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: mtc1 $[[AND]], $f0
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; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
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; 32R2: mtc1 $[[INS]], $f0
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; NO-NAN: abs.s
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%call = tail call float @fabsf(float %a) nounwind readnone
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ret float %call
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}
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declare float @fabsf(float) nounwind readnone
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define double @foo1(double %a) nounwind readnone {
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entry:
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: mtc1 $[[AND]], $f1
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; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
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; 32R2: mtc1 $[[INS]], $f1
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63
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; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
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; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: dmtc1 $[[AND]], $f0
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; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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; NO-NAN: abs.d
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%call = tail call double @fabs(double %a) nounwind readnone
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ret double %call
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}
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declare double @fabs(double) nounwind readnone
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