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[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
Each of the cases marked as legal here have an imported pattern in AArch64GenGlobalISel.inc. So, if we mark them as legal, we get selection for free. Technically this is only supposed to happen if we have NEON support. But, we fall back if we don't have that in the legalizer right now. I suppose it'd be better to have a FIXME so we can write the testcase when the time comes. (Plus, it'd just fall back in selection if NEON isn't available, so it's not *wrong*, I guess?) This fixes some fallbacks in the test suite. (Also use `isScalar` from LegalityPredicates.cpp while we're here just to tidy things a little bit.) Differential Revision: https://reviews.llvm.org/D100916
This commit is contained in:
Jessica Paquette
parent
29e34b908b
commit
11b294d082
@ -686,8 +686,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_BZERO, G_MEMCPY, G_MEMMOVE, G_MEMSET})
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.libcall();
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getActionDefinitionsBuilder(G_ABS).lowerIf(
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[=](const LegalityQuery &Query) { return Query.Types[0].isScalar(); });
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// FIXME: Legal types are only legal with NEON.
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getActionDefinitionsBuilder(G_ABS)
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.lowerIf(isScalar(0))
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.legalFor(PackedVectorAllTypeList);
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getActionDefinitionsBuilder(G_VECREDUCE_FADD)
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// We only have FADDP to do reduction-like operations. Lower the rest.
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@ -32,3 +32,117 @@ body: |
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%1:_(s64) = G_ABS %0(s64)
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$x0 = COPY %1(s64)
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...
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---
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name: abs_v4s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<4 x s16>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<4 x s16>) = COPY $d0
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%1:_(<4 x s16>) = G_ABS %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v8s16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v8s16
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<8 x s16>) = COPY $q0
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%1:_(<8 x s16>) = G_ABS %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: abs_v2s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = G_ABS %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v4s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v4s32
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = G_ABS %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: abs_v4s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: abs_v4s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
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; CHECK: $d0 = COPY [[ABS]](<8 x s8>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = G_ABS %0
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$d0 = COPY %1(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: abs_v16s8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: abs_v16s8
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
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; CHECK: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
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; CHECK: $q0 = COPY [[ABS]](<16 x s8>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<16 x s8>) = COPY $q0
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%1:_(<16 x s8>) = G_ABS %0
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$q0 = COPY %1(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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130
test/CodeGen/AArch64/GlobalISel/select-abs.mir
Normal file
130
test/CodeGen/AArch64/GlobalISel/select-abs.mir
Normal file
@ -0,0 +1,130 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-apple-ios -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: v4s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[ABSv4i16_:%[0-9]+]]:fpr64 = ABSv4i16 [[COPY]]
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; CHECK: $d0 = COPY [[ABSv4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_ABS %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v8s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[ABSv8i16_:%[0-9]+]]:fpr128 = ABSv8i16 [[COPY]]
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; CHECK: $q0 = COPY [[ABSv8i16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_ABS %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[ABSv2i32_:%[0-9]+]]:fpr64 = ABSv2i32 [[COPY]]
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; CHECK: $d0 = COPY [[ABSv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_ABS %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v4s32
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[ABSv4i32_:%[0-9]+]]:fpr128 = ABSv4i32 [[COPY]]
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; CHECK: $q0 = COPY [[ABSv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_ABS %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v4s8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[ABSv8i8_:%[0-9]+]]:fpr64 = ABSv8i8 [[COPY]]
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; CHECK: $d0 = COPY [[ABSv8i8_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s8>) = G_ABS %0
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$d0 = COPY %1(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v16s8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v16s8
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[ABSv16i8_:%[0-9]+]]:fpr128 = ABSv16i8 [[COPY]]
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; CHECK: $q0 = COPY [[ABSv16i8_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = G_ABS %0
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$q0 = COPY %1(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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