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Convert assert(0) to llvm_unreachable

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llvm-svn: 149961
This commit is contained in:
Craig Topper 2012-02-07 02:50:20 +00:00
parent 085bdb73fa
commit 11bcb12b5e
42 changed files with 106 additions and 151 deletions
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20
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -84,6 +84,7 @@ namespace {
void EmitTextAttribute(unsigned Attribute, StringRef String) {
switch (Attribute) {
default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
case ARMBuildAttrs::CPU_name:
Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
break;
@ -92,7 +93,6 @@ namespace {
case ARMBuildAttrs::VFP_arch:
Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
break;
default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
}
}
void Finish() { }
@ -196,6 +196,7 @@ namespace {
AttributeItemType item = Contents[i];
Streamer.EmitULEB128IntValue(item.Tag, 0);
switch (item.Type) {
default: llvm_unreachable("Invalid attribute type");
case AttributeItemType::NumericAttribute:
Streamer.EmitULEB128IntValue(item.IntValue, 0);
break;
@ -203,8 +204,6 @@ namespace {
Streamer.EmitBytes(item.StringValue.upper(), 0);
Streamer.EmitIntValue(0, 1); // '\0'
break;
default:
assert(0 && "Invalid attribute type");
}
}
@ -331,8 +330,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned TF = MO.getTargetFlags();
switch (MO.getType()) {
default:
assert(0 && "<unknown operand type>");
default: llvm_unreachable("<unknown operand type>");
case MachineOperand::MO_Register: {
unsigned Reg = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
@ -1118,7 +1116,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
switch (Opc) {
default:
MI->dump();
assert(0 && "Unsupported opcode for unwinding information");
llvm_unreachable("Unsupported opcode for unwinding information");
case ARM::tPUSH:
// Special case here: no src & dst reg, but two extra imp ops.
StartOp = 2; NumOffset = 2;
@ -1147,7 +1145,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
switch (Opc) {
default:
MI->dump();
assert(0 && "Unsupported opcode for unwinding information");
llvm_unreachable("Unsupported opcode for unwinding information");
case ARM::MOVr:
case ARM::tMOVr:
Offset = 0;
@ -1194,16 +1192,16 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
OutStreamer.EmitPad(Offset);
} else {
MI->dump();
assert(0 && "Unsupported opcode for unwinding information");
llvm_unreachable("Unsupported opcode for unwinding information");
}
} else if (DstReg == ARM::SP) {
// FIXME: .movsp goes here
MI->dump();
assert(0 && "Unsupported opcode for unwinding information");
llvm_unreachable("Unsupported opcode for unwinding information");
}
else {
MI->dump();
assert(0 && "Unsupported opcode for unwinding information");
llvm_unreachable("Unsupported opcode for unwinding information");
}
}
}
@ -1232,7 +1230,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Check for manual lowerings.
unsigned Opc = MI->getOpcode();
switch (Opc) {
case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
case ARM::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
SmallString<128> TmpStr;

4
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -156,9 +156,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned OffImm = MI->getOperand(NumOps-2).getImm();
ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
switch (AddrMode) {
default:
assert(false && "Unknown indexed op!");
return NULL;
default: llvm_unreachable("Unknown indexed op!");
case ARMII::AddrMode2: {
bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
unsigned Amt = ARM_AM::getAM2Offset(OffImm);

3
lib/Target/ARM/ARMConstantPoolValue.cpp
View File

@ -62,8 +62,7 @@ const char *ARMConstantPoolValue::getModifierText() const {
int ARMConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment) {
assert(false && "Shouldn't be calling this directly!");
return -1;
llvm_unreachable("Shouldn't be calling this directly!");
}
void

24
lib/Target/ARM/ARMELFWriterInfo.cpp
View File

@ -41,8 +41,8 @@ unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
case ARM::reloc_arm_machine_cp_entry:
case ARM::reloc_arm_jt_base:
case ARM::reloc_arm_pic_jt:
assert(0 && "unsupported ARM relocation type"); return 0;
llvm_unreachable("unsupported ARM relocation type");
case ARM::reloc_arm_branch: return ELF::R_ARM_CALL;
case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS;
case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC;
@ -53,30 +53,26 @@ unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
long int Modifier) const {
assert(0 && "ARMELFWriterInfo::getDefaultAddendForRelTy() not implemented");
return 0;
llvm_unreachable("ARMELFWriterInfo::getDefaultAddendForRelTy() not "
"implemented");
}
unsigned ARMELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
assert(0 && "ARMELFWriterInfo::getRelocationTySize() not implemented");
return 0;
llvm_unreachable("ARMELFWriterInfo::getRelocationTySize() not implemented");
}
bool ARMELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
assert(0 && "ARMELFWriterInfo::isPCRelativeRel() not implemented");
return 1;
llvm_unreachable("ARMELFWriterInfo::isPCRelativeRel() not implemented");
}
unsigned ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
assert(0 &&
"ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
return 0;
llvm_unreachable("ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not "
"implemented");
}
long int ARMELFWriterInfo::computeRelocation(unsigned SymOffset,
unsigned RelOffset,
unsigned RelTy) const {
assert(0 &&
"ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not implemented");
return 0;
llvm_unreachable("ARMELFWriterInfo::getAbsoluteLabelMachineRelTy() not "
"implemented");
}

4
lib/Target/ARM/ARMFastISel.cpp
View File

@ -881,9 +881,7 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
bool needsLowering = false;
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Unhandled load/store type!");
break;
default: llvm_unreachable("Unhandled load/store type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:

3
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -2361,8 +2361,7 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: assert(false && "Illegal conditional move type!");
break;
default: llvm_unreachable("Illegal conditional move type!");
case MVT::i32:
Opc = Subtarget->isThumb()
? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)

17
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -3070,8 +3070,7 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
unsigned Opc;
switch (Op.getOpcode()) {
default:
assert(0 && "Invalid opcode!");
default: llvm_unreachable("Invalid opcode!");
case ISD::FP_TO_SINT:
Opc = ARMISD::FTOSI;
break;
@ -3101,8 +3100,7 @@ static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
unsigned CastOpc;
unsigned Opc;
switch (Op.getOpcode()) {
default:
assert(0 && "Invalid opcode!");
default: llvm_unreachable("Invalid opcode!");
case ISD::SINT_TO_FP:
CastOpc = ISD::SIGN_EXTEND;
Opc = ISD::SINT_TO_FP;
@ -3126,8 +3124,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
unsigned Opc;
switch (Op.getOpcode()) {
default:
assert(0 && "Invalid opcode!");
default: llvm_unreachable("Invalid opcode!");
case ISD::SINT_TO_FP:
Opc = ARMISD::SITOF;
break;
@ -4957,7 +4954,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
unsigned Opc;
bool ExtraOp = false;
switch (Op.getOpcode()) {
default: assert(0 && "Invalid code");
default: llvm_unreachable("Invalid code");
case ISD::ADDC: Opc = ARMISD::ADDC; break;
case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
case ISD::SUBC: Opc = ARMISD::SUBC; break;
@ -6667,7 +6664,7 @@ static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
default:
assert(0 && "Invalid vector element type for padd optimization.");
llvm_unreachable("Invalid vector element type for padd optimization.");
}
SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
@ -7332,7 +7329,7 @@ static SDValue CombineBaseUpdate(SDNode *N,
if (isIntrinsic) {
unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (IntNo) {
default: assert(0 && "unexpected intrinsic for Neon base update");
default: llvm_unreachable("unexpected intrinsic for Neon base update");
case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
NumVecs = 1; break;
case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
@ -7365,7 +7362,7 @@ static SDValue CombineBaseUpdate(SDNode *N,
} else {
isLaneOp = true;
switch (N->getOpcode()) {
default: assert(0 && "unexpected opcode for Neon base update");
default: llvm_unreachable("unexpected opcode for Neon base update");
case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;

7
lib/Target/ARM/ARMMCInstLower.cpp
View File

@ -31,8 +31,7 @@ MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
OutContext);
switch (MO.getTargetFlags()) {
default:
assert(0 && "Unknown target flag on symbol operand");
default: llvm_unreachable("Unknown target flag on symbol operand");
case 0:
break;
case ARMII::MO_LO16:
@ -67,9 +66,7 @@ MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
MCOperand &MCOp) {
switch (MO.getType()) {
default:
assert(0 && "unknown operand type");
return false;
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all non-CPSR implicit register operands.
if (MO.isImplicit() && MO.getReg() != ARM::CPSR)

8
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2725,7 +2725,7 @@ static unsigned getNextRegister(unsigned Reg) {
if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
return Reg + 1;
switch(Reg) {
default: assert(0 && "Invalid GPR number!");
default: llvm_unreachable("Invalid GPR number!");
case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
@ -5222,7 +5222,7 @@ validateInstruction(MCInst &Inst,
static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
default: llvm_unreachable("unexpected opcode!");
// VST1LN
case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
@ -5331,7 +5331,7 @@ static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
default: llvm_unreachable("unexpected opcode!");
// VLD1LN
case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
@ -7022,7 +7022,7 @@ processInstruction(MCInst &Inst,
ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
if (SOpc == ARM_AM::rrx) return false;
switch (Inst.getOpcode()) {
default: assert(0 && "unexpected opcode!");
default: llvm_unreachable("unexpected opcode!");
case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
case ARM::EORrsi: newOpc = ARM::EORrr; break;

2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -533,7 +533,7 @@ static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
MI.addOperand(MCOperand::CreateExpr(Expr));
else
assert(0 && "bad SymbolicOp.VariantKind");
llvm_unreachable("bad SymbolicOp.VariantKind");
return true;
}

4
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -645,7 +645,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
if (getAvailableFeatures() & ARM::FeatureMClass) {
switch (Op.getImm()) {
default: assert(0 && "Unexpected mask value!");
default: llvm_unreachable("Unexpected mask value!");
case 0: O << "apsr"; return;
case 1: O << "iapsr"; return;
case 2: O << "eapsr"; return;
@ -668,7 +668,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
O << "APSR_";
switch (Mask) {
default: assert(0);
default: llvm_unreachable("Unexpected mask value!");
case 4: O << "g"; return;
case 8: O << "nzcvq"; return;
case 12: O << "nzcvqg"; return;

9
lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
View File

@ -16,6 +16,7 @@
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
@ -43,7 +44,7 @@ namespace ARM_AM {
static inline const char *getShiftOpcStr(ShiftOpc Op) {
switch (Op) {
default: assert(0 && "Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return "asr";
case ARM_AM::lsl: return "lsl";
case ARM_AM::lsr: return "lsr";
@ -54,7 +55,7 @@ namespace ARM_AM {
static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
switch (Op) {
default: assert(0 && "Unknown shift opc!");
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::asr: return 2;
case ARM_AM::lsl: return 0;
case ARM_AM::lsr: return 1;
@ -72,7 +73,7 @@ namespace ARM_AM {
static inline const char *getAMSubModeStr(AMSubMode Mode) {
switch (Mode) {
default: assert(0 && "Unknown addressing sub-mode!");
default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::ia: return "ia";
case ARM_AM::ib: return "ib";
case ARM_AM::da: return "da";
@ -569,7 +570,7 @@ namespace ARM_AM {
}
EltBits = 64;
} else {
assert(false && "Unsupported NEON immediate");
llvm_unreachable("Unsupported NEON immediate");
}
return Val;
}

8
lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
View File

@ -163,7 +163,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
unsigned Type = 0;
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
default: assert(0 && "Unimplemented");
default: llvm_unreachable("Unimplemented");
case FK_Data_4:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
@ -171,8 +171,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
Type = ELF::R_ARM_REL32;
break;
case MCSymbolRefExpr::VK_ARM_TLSGD:
assert(0 && "unimplemented");
break;
llvm_unreachable("unimplemented");
case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
Type = ELF::R_ARM_TLS_IE32;
break;
@ -248,8 +247,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case ARM::fixup_arm_thumb_cb:
case ARM::fixup_arm_thumb_cp:
case ARM::fixup_arm_thumb_br:
assert(0 && "Unimplemented");
break;
llvm_unreachable("Unimplemented");
case ARM::fixup_arm_uncondbranch:
Type = ELF::R_ARM_CALL;
break;

6
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -166,7 +166,7 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const {
ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
switch (Mode) {
default: assert(0 && "Unknown addressing sub-mode!");
default: llvm_unreachable("Unknown addressing sub-mode!");
case ARM_AM::da: return 0;
case ARM_AM::ia: return 1;
case ARM_AM::db: return 2;
@ -832,7 +832,7 @@ getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
// but this is good enough for now.
static bool EvaluateAsPCRel(const MCExpr *Expr) {
switch (Expr->getKind()) {
default: assert(0 && "Unexpected expression type");
default: llvm_unreachable("Unexpected expression type");
case MCExpr::SymbolRef: return false;
case MCExpr::Binary: return true;
}
@ -856,7 +856,7 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
MCFixupKind Kind;
switch (ARM16Expr->getKind()) {
default: assert(0 && "Unsupported ARMFixup");
default: llvm_unreachable("Unsupported ARMFixup");
case ARMMCExpr::VK_ARM_HI16:
if (!isTargetDarwin() && EvaluateAsPCRel(E))
Kind = MCFixupKind(isThumb2()

5
lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
View File

@ -21,7 +21,7 @@ ARMMCExpr::Create(VariantKind Kind, const MCExpr *Expr,
void ARMMCExpr::PrintImpl(raw_ostream &OS) const {
switch (Kind) {
default: assert(0 && "Invalid kind!");
default: llvm_unreachable("Invalid kind!");
case VK_ARM_HI16: OS << ":upper16:"; break;
case VK_ARM_LO16: OS << ":lower16:"; break;
}
@ -45,8 +45,7 @@ ARMMCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
static void AddValueSymbols_(const MCExpr *Value, MCAssembler *Asm) {
switch (Value->getKind()) {
case MCExpr::Target:
assert(0 && "Can't handle nested target expr!");
break;
llvm_unreachable("Can't handle nested target expr!");
case MCExpr::Constant:
break;

2
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -694,7 +694,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// register. The offset is already handled in the vreg value.
MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
} else {
assert(false && "Unexpected opcode!");
llvm_unreachable("Unexpected opcode!");
}
// Add predicate back if it's needed.

6
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -2033,8 +2033,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
int elt_byte = EltNo * VT.getSizeInBits() / 8;
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
default: llvm_unreachable("Invalid value type!");
case MVT::i8: {
prefslot_begin = prefslot_end = 3;
break;
@ -2362,8 +2361,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Invalid value type!");
default: llvm_unreachable("Invalid value type!");
case MVT::i8: {
SDValue N = Op.getOperand(0);
SDValue Elt0 = DAG.getConstant(0, MVT::i32);

2
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -1356,7 +1356,7 @@ void CppWriter::printInstruction(const Instruction *I,
case Instruction::PtrToInt: Out << "PtrToIntInst"; break;
case Instruction::IntToPtr: Out << "IntToPtrInst"; break;
case Instruction::BitCast: Out << "BitCastInst"; break;
default: assert(0 && "Unreachable"); break;
default: llvm_unreachable("Unreachable");
}
Out << "(" << opNames[0] << ", "
<< getCppName(cst->getType()) << ", \"";

6
lib/Target/Hexagon/HexagonAsmPrinter.cpp
View File

@ -318,14 +318,14 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
if (Base.isReg())
printOperand(MI, OpNo, O);
else
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
if (Offset.isImm()) {
if (Offset.getImm())
O << " + #" << Offset.getImm();
}
else
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
return false;
}
@ -333,7 +333,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI,
unsigned OpNo,
raw_ostream &O) {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}

2
lib/Target/Hexagon/HexagonCFGOptimizer.cpp
View File

@ -84,7 +84,7 @@ HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
break;
default:
assert(0 && "Cannot handle this case");
llvm_unreachable("Cannot handle this case");
}
MI->setDesc(QII->get(NewOpcode));

4
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -1099,7 +1099,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
ReplaceUses(N, RsPd);
return RsPd;
}
assert(0 && "Unexpected value type");
llvm_unreachable("Unexpected value type");
}
}
return SelectCode(N);
@ -1145,7 +1145,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
Ops.push_back(SDVal);
} else {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}
}
EVT ReturnValueVT = N->getValueType(0);

14
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -449,7 +449,7 @@ HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
switch (VA.getLocInfo()) {
default:
// Loc info must be one of Full, SExt, ZExt, or AExt.
assert(0 && "Unknown loc info!");
llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::SExt:
@ -1345,12 +1345,12 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
SDValue
HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
default: llvm_unreachable("Should not custom lower this!");
// Frame & Return address. Currently unimplemented.
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GlobalTLSAddress:
assert(0 && "TLS not implemented for Hexagon.");
llvm_unreachable("TLS not implemented for Hexagon.");
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
@ -1382,10 +1382,8 @@ const {
FuncInfo->addAllocaAdjustInst(MI);
return BB;
}
default:
assert(false && "Unexpected instr type to insert");
default: llvm_unreachable("Unexpected instr type to insert");
} // switch
return NULL;
}
//===----------------------------------------------------------------------===//
@ -1401,7 +1399,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
case 'r': // R0-R31
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i32:
case MVT::i16:
case MVT::i8:
@ -1410,7 +1408,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
}
default:
assert(0 && "Unknown asm register class");
llvm_unreachable("Unknown asm register class");
}
}

15
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -383,7 +383,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
} else {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}
}
@ -395,8 +395,7 @@ void HexagonInstrInfo::storeRegToAddr(
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
assert(0 && "Unimplemented");
return;
llvm_unreachable("Unimplemented");
}
@ -427,7 +426,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else {
assert(0 && "Can't store this register to stack slot");
llvm_unreachable("Can't store this register to stack slot");
}
}
@ -436,7 +435,7 @@ void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
assert(0 && "Unimplemented");
llvm_unreachable("Unimplemented");
}
@ -823,7 +822,7 @@ PredicateInstruction(MachineInstr *MI,
} else if (MO.isImm()) {
MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
} else {
assert(false && "Unexpected operand type");
llvm_unreachable("Unexpected operand type");
}
}
@ -1269,10 +1268,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {
return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
Offset <= Hexagon_MEMB_AUTOINC_MAX);
}
assert(0 && "Not an auto-inc opc!");
return false;
llvm_unreachable("Not an auto-inc opc!");
}

8
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -125,7 +125,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
} else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
// Hexagon_TODO: add code
} else {
assert(0 && "Cannot handle this call frame pseudo instruction");
llvm_unreachable("Cannot handle this call frame pseudo instruction");
}
MBB.erase(I);
}
@ -305,13 +305,11 @@ void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove>
}
unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
assert(0 && "What is the exception register");
return 0;
llvm_unreachable("What is the exception register");
}
unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
assert(0 && "What is the exception handler register");
return 0;
llvm_unreachable("What is the exception handler register");
}
#define GET_REGINFO_TARGET_DESC

4
lib/Target/MBlaze/MBlazeELFWriterInfo.cpp
View File

@ -102,8 +102,6 @@ long int MBlazeELFWriterInfo::computeRelocation(unsigned SymOffset,
unsigned RelTy) const {
if (RelTy == ELF::R_MICROBLAZE_32_PCREL || ELF::R_MICROBLAZE_64_PCREL)
return SymOffset - (RelOffset + 4);
else
assert(0 && "computeRelocation unknown for this relocation type");
return 0;
llvm_unreachable("computeRelocation unknown for this relocation type");
}

2
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -216,7 +216,7 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB)
const {
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
default: llvm_unreachable("Unexpected instr type to insert");
case MBlaze::ShiftRL:
case MBlaze::ShiftRA:

4
lib/Target/MBlaze/MBlazeMCInstLower.cpp
View File

@ -85,9 +85,7 @@ GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
MCSymbol *MBlazeMCInstLower::
GetBlockAddressSymbol(const MachineOperand &MO) const {
switch (MO.getTargetFlags()) {
default:
assert(0 && "Unknown target flag on GV operand");
default: llvm_unreachable("Unknown target flag on GV operand");
case 0: break;
}

2
lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp
View File

@ -27,7 +27,7 @@ using namespace llvm;
static unsigned getFixupKindSize(unsigned Kind) {
switch (Kind) {
default: assert(0 && "invalid fixup kind!");
default: llvm_unreachable("invalid fixup kind!");
case FK_Data_1: return 1;
case FK_PCRel_2:
case FK_Data_2: return 2;

4
lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp
View File

@ -54,8 +54,8 @@ public:
static unsigned GetMBlazeRegNum(const MCOperand &MO) {
// FIXME: getMBlazeRegisterNumbering() is sufficient?
assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented.");
return 0;
llvm_unreachable("MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet "
"implemented.");
}
void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {

2
lib/Target/MSP430/MSP430AsmPrinter.cpp
View File

@ -65,7 +65,7 @@ void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
raw_ostream &O, const char *Modifier) {
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
default: assert(0 && "Not implemented yet!");
default: llvm_unreachable("Not implemented yet!");
case MachineOperand::MO_Register:
O << MSP430InstPrinter::getRegisterName(MO.getReg());
return;

6
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -593,8 +593,7 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
// Expand non-constant shifts to loops:
if (!isa<ConstantSDNode>(N->getOperand(1)))
switch (Opc) {
default:
assert(0 && "Invalid shift opcode!");
default: llvm_unreachable("Invalid shift opcode!");
case ISD::SHL:
return DAG.getNode(MSP430ISD::SHL, dl,
VT, N->getOperand(0), N->getOperand(1));
@ -1022,8 +1021,7 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
unsigned Opc;
const TargetRegisterClass * RC;
switch (MI->getOpcode()) {
default:
assert(0 && "Invalid shift opcode!");
default: llvm_unreachable("Invalid shift opcode!");
case MSP430::Shl8:
Opc = MSP430::SHL8r1;
RC = MSP430::GR8RegisterClass;

10
lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -130,9 +130,7 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
switch (CC) {
default:
assert(0 && "Invalid branch condition!");
break;
default: llvm_unreachable("Invalid branch condition!");
case MSP430CC::COND_E:
CC = MSP430CC::COND_NE;
break;
@ -297,8 +295,7 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
switch (Desc.TSFlags & MSP430II::SizeMask) {
default:
switch (Desc.getOpcode()) {
default:
assert(0 && "Unknown instruction size!");
default: llvm_unreachable("Unknown instruction size!");
case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::IMPLICIT_DEF:
@ -314,8 +311,7 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
}
case MSP430II::SizeSpecial:
switch (MI->getOpcode()) {
default:
assert(0 && "Unknown instruction size!");
default: llvm_unreachable("Unknown instruction size!");
case MSP430::SAR8r1c:
case MSP430::SAR16r1c:
return 4;

6
lib/Target/MSP430/MSP430MCInstLower.cpp
View File

@ -39,7 +39,7 @@ GetGlobalAddressSymbol(const MachineOperand &MO) const {
MCSymbol *MSP430MCInstLower::
GetExternalSymbolSymbol(const MachineOperand &MO) const {
switch (MO.getTargetFlags()) {
default: assert(0 && "Unknown target flag on GV operand");
default: llvm_unreachable("Unknown target flag on GV operand");
case 0: break;
}
@ -81,7 +81,7 @@ GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
MCSymbol *MSP430MCInstLower::
GetBlockAddressSymbol(const MachineOperand &MO) const {
switch (MO.getTargetFlags()) {
default: assert(0 && "Unknown target flag on GV operand");
default: llvm_unreachable("Unknown target flag on GV operand");
case 0: break;
}
@ -116,7 +116,7 @@ void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
switch (MO.getType()) {
default:
MI->dump();
assert(0 && "unknown operand type");
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;

2
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
View File

@ -92,7 +92,7 @@ static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
switch (Kind) {
default: assert(0 && "Invalid kind!");
default: llvm_unreachable("Invalid kind!");
case MCSymbolRefExpr::VK_None: break;
case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break;
case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break;

4
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -810,9 +810,7 @@ MachineBasicBlock *
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
switch (MI->getOpcode()) {
default:
assert(false && "Unexpected instr type to insert");
return NULL;
default: llvm_unreachable("Unexpected instr type to insert");
case Mips::ATOMIC_LOAD_ADD_I8:
case Mips::ATOMIC_LOAD_ADD_I8_P8:
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);

8
lib/Target/Mips/MipsMCInstLower.cpp
View File

@ -37,7 +37,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
const MCSymbol *Symbol;
switch(MO.getTargetFlags()) {
default: assert(0 && "Invalid target flag!");
default: llvm_unreachable("Invalid target flag!");
case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
@ -176,9 +176,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
MachineOperandType MOTy = MO.getType();
switch (MOTy) {
default:
assert(0 && "unknown operand type");
break;
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) break;
@ -315,7 +313,7 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
}
default:
// FIXME: need to add others
assert(0 && "unaligned instruction not processed");
llvm_unreachable("unaligned instruction not processed");
}
MCInsts.push_back(Instr1);

4
lib/Target/PTX/PTXInstrInfo.cpp
View File

@ -300,7 +300,7 @@ void PTXInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
assert(false && "storeRegToStackSlot should not be called for PTX");
llvm_unreachable("storeRegToStackSlot should not be called for PTX");
}
void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@ -308,7 +308,7 @@ void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
assert(false && "loadRegFromStackSlot should not be called for PTX");
llvm_unreachable("loadRegFromStackSlot should not be called for PTX");
}
// static helper routines

2
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
View File

@ -174,7 +174,7 @@ void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
unsigned CCReg = MI->getOperand(OpNo).getReg();
unsigned RegNo;
switch (CCReg) {
default: assert(0 && "Unknown CR register");
default: llvm_unreachable("Unknown CR register");
case PPC::CR0: RegNo = 0; break;
case PPC::CR1: RegNo = 1; break;
case PPC::CR2: RegNo = 2; break;

7
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
View File

@ -92,14 +92,13 @@ public:
const MCInstFragment *DF,
const MCAsmLayout &Layout) const {
// FIXME.
assert(0 && "relaxInstruction() unimplemented");
return false;
llvm_unreachable("relaxInstruction() unimplemented");
}
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
// FIXME.
assert(0 && "relaxInstruction() unimplemented");
llvm_unreachable("relaxInstruction() unimplemented");
}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
@ -128,7 +127,7 @@ namespace {
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value) const {
assert(0 && "UNIMP");
llvm_unreachable("UNIMP");
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {

3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -4578,8 +4578,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default:
assert(false && "Do not know how to custom type legalize this operation!");
return;
llvm_unreachable("Do not know how to custom type legalize this operation!");
case ISD::VAARG: {
if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
|| TM.getSubtarget<PPCSubtarget>().isPPC64())

2
lib/Target/PowerPC/PPCMCInstLower.cpp
View File

@ -140,7 +140,7 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
switch (MO.getType()) {
default:
MI->dump();
assert(0 && "unknown operand type");
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::CreateReg(MO.getReg());

2
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -142,7 +142,7 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
std::string operand = "";
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
default: assert(0 && "Operand is not a register ");
default: llvm_unreachable("Operand is not a register");
case MachineOperand::MO_Register:
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Operand is not a physical register ");