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https://github.com/RPCS3/llvm-mirror.git
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Give V8 select_cc, in the spirit of the PPC backend
llvm-svn: 24823
This commit is contained in:
Chris Lattner
parent
6d46ed50a0
commit
11fa3cc8ee
@ -16,6 +16,7 @@
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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@ -40,6 +41,9 @@ namespace V8ISD {
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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SELECT_ICC, // Select between two values using the current ICC flags.
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SELECT_FCC, // Select between two values using the current FCC flags.
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};
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}
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@ -66,6 +70,8 @@ namespace {
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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};
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}
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@ -82,9 +88,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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@ -116,6 +122,10 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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computeRegisterProperties();
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}
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@ -243,22 +253,6 @@ SDOperand SparcV8TargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Should not custom lower this!");
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand CC = Op.getOperand(1);
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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// Get the condition flag.
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if (LHS.getValueType() == MVT::i32) {
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SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
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} else {
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SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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}
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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@ -298,10 +292,134 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Convert the int value to FP in an FP register.
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return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
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}
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case ISD::BR_CC: {
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SDOperand Chain = Op.getOperand(0);
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SDOperand CC = Op.getOperand(1);
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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// Get the condition flag.
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if (LHS.getValueType() == MVT::i32) {
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SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
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} else {
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SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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}
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}
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case ISD::SELECT_CC: {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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unsigned Opc;
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Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
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SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
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Opc = LHS.getValueType() == MVT::i32 ?
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V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
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return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
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DAG.getConstant(CC, MVT::i32), CompareFlag);
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}
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}
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}
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MachineBasicBlock *
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SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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unsigned BROpcode;
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// Figure out the conditional branch opcode to use for this select_cc.
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown SELECT_CC!");
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case V8::SELECT_CC_Int_ICC:
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case V8::SELECT_CC_FP_ICC:
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case V8::SELECT_CC_DFP_ICC:
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// Integer compare.
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switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
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default: assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: BROpcode = V8::BE; break;
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case ISD::SETNE: BROpcode = V8::BNE; break;
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case ISD::SETLT: BROpcode = V8::BL; break;
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case ISD::SETGT: BROpcode = V8::BG; break;
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case ISD::SETLE: BROpcode = V8::BLE; break;
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case ISD::SETGE: BROpcode = V8::BGE; break;
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case ISD::SETULT: BROpcode = V8::BCS; break;
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case ISD::SETULE: BROpcode = V8::BLEU; break;
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case ISD::SETUGT: BROpcode = V8::BGU; break;
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case ISD::SETUGE: BROpcode = V8::BCC; break;
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}
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break;
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case V8::SELECT_CC_Int_FCC:
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case V8::SELECT_CC_FP_FCC:
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case V8::SELECT_CC_DFP_FCC:
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// FP compare.
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switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
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default: assert(0 && "Unknown fp condition code!");
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case ISD::SETEQ: BROpcode = V8::FBE; break;
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case ISD::SETNE: BROpcode = V8::FBNE; break;
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case ISD::SETLT: BROpcode = V8::FBL; break;
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case ISD::SETGT: BROpcode = V8::FBG; break;
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case ISD::SETLE: BROpcode = V8::FBLE; break;
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case ISD::SETGE: BROpcode = V8::FBGE; break;
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case ISD::SETULT: BROpcode = V8::FBUL; break;
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case ISD::SETULE: BROpcode = V8::FBULE; break;
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case ISD::SETUGT: BROpcode = V8::FBUG; break;
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case ISD::SETUGE: BROpcode = V8::FBUGE; break;
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case ISD::SETUO: BROpcode = V8::FBU; break;
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case ISD::SETO: BROpcode = V8::FBO; break;
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case ISD::SETONE: BROpcode = V8::FBLG; break;
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case ISD::SETUEQ: BROpcode = V8::FBUE; break;
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}
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break;
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}
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// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// [f]bCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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@ -77,7 +77,10 @@ def SDTV8cmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8brcc :
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
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SDTCisVT<2, FlagVT>]>;
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SDTCisVT<2, FlagVT>]>;
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def SDTV8selectcc :
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SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
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def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
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def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
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@ -90,25 +93,61 @@ def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
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def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>;
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def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
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def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
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def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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class PseudoInstV8<string asmstr, dag ops> : InstV8 {
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class Pseudo<dag ops, string asmstr, list<dag> pattern> : InstV8 {
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let AsmString = asmstr;
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dag OperandList = ops;
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let Pattern = pattern;
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}
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def PHI : Pseudo<(ops variable_ops), "PHI", []>;
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def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
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def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
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def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
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"!FpMOVD", []>; // pseudo 64-bit double move
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence. This has to handle all permutations of
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// selection between i32/f32/f64 on ICC and FCC.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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def SELECT_CC_Int_ICC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond, ICC))]>;
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def SELECT_CC_Int_FCC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond, FCC))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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[(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
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imm:$Cond, ICC))]>;
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def SELECT_CC_FP_FCC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_FCC PSEUDO!",
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[(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
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imm:$Cond, FCC))]>;
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def SELECT_CC_DFP_ICC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_ICC PSEUDO!",
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[(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond, ICC))]>;
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def SELECT_CC_DFP_FCC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_FCC PSEUDO!",
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[(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond, FCC))]>;
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}
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def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
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def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
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(ops i32imm:$amt)>;
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def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
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(ops i32imm:$amt)>;
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//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
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def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
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(ops IntRegs:$dst)>;
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def FpMOVD : PseudoInstV8<"!FpMOVD", // pseudo 64-bit double move
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(ops DFPRegs:$dst, DFPRegs:$src)>;
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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