mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Make the type of shift amount i32 in order to reduce the number of shift
instruction definitions. llvm-svn: 143989
This commit is contained in:
parent
89c8797a02
commit
11fea5de78
@ -32,7 +32,7 @@ def Subtract32 : SDNodeXForm<imm, [{
|
||||
def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
|
||||
|
||||
// imm32_63 predicate - True if imm is in range [32, 63].
|
||||
def imm32_63 : ImmLeaf<i64,
|
||||
def imm32_63 : ImmLeaf<i32,
|
||||
[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
|
||||
Subtract32>;
|
||||
|
||||
@ -43,12 +43,12 @@ def imm32_63 : ImmLeaf<i64,
|
||||
// 64-bit shift instructions.
|
||||
class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
|
||||
SDNode OpNode>:
|
||||
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5_64, shamt_64,
|
||||
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
|
||||
CPU64Regs>;
|
||||
|
||||
class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
|
||||
SDNode OpNode>:
|
||||
shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64,
|
||||
shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
|
||||
CPU64Regs>;
|
||||
|
||||
// Mul, Div
|
||||
|
@ -98,6 +98,8 @@ namespace llvm {
|
||||
public:
|
||||
explicit MipsTargetLowering(MipsTargetMachine &TM);
|
||||
|
||||
virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
||||
|
||||
virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
|
||||
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
|
@ -327,9 +327,9 @@ class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
|
||||
|
||||
class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
|
||||
SDNode OpNode, RegisterClass RC>:
|
||||
FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
|
||||
FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
|
||||
!strconcat(instr_asm, "\t$rd, $rt, $rs"),
|
||||
[(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> {
|
||||
[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
|
||||
let shamt = isRotate;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user