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[AArch64] Adjust the cost model for Exynos M3

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Fix the modeling of long division and SIMD conversion from integer and
horizontal minimum and maximum.

llvm-svn: 324417
This commit is contained in:
Evandro Menezes 2018-02-06 22:35:47 +00:00
parent c610726680
commit 120280b132
1 changed files with 4 additions and 4 deletions
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8
lib/Target/AArch64/AArch64SchedExynosM3.td
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@ -198,8 +198,8 @@ def : WriteRes<WriteID32, [M3UnitC,
M3UnitD]> { let Latency = 12;
let ResourceCycles = [1, 12]; }
def : WriteRes<WriteID64, [M3UnitC,
M3UnitD]> { let Latency = 12;
let ResourceCycles = [1, 12]; }
M3UnitD]> { let Latency = 21;
let ResourceCycles = [1, 21]; }
def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
let ResourceCycles = [2]; }
@ -304,7 +304,7 @@ def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR,
let NumMicroOps = 1;
let ResourceCycles = [26]; }
def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC,
M3UnitNMSC]> { let Latency = 4;
M3UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2; }
def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; }
def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; }
@ -608,7 +608,7 @@ def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>;
def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>;
def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>;
def : InstRW<[M3WriteFCVT3], (instregex "^[SU]CVTFv")>;
def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>;
def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>;
def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>;