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Use PairDRegs to implement ConcatVectors. No functionality change.
llvm-svn: 122017
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@ -2141,13 +2141,7 @@ SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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if (!VT.is128BitVector() || N->getNumOperands() != 2)
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if (!VT.is128BitVector() || N->getNumOperands() != 2)
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llvm_unreachable("unexpected CONCAT_VECTORS");
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llvm_unreachable("unexpected CONCAT_VECTORS");
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DebugLoc dl = N->getDebugLoc();
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return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
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SDValue V0 = N->getOperand(0);
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SDValue V1 = N->getOperand(1);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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}
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}
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SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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