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[x86] Teach the target-specific combining how to aggressively fold
half-shuffles, even looking through intervening instructions in a chain. Summary: This doesn't happen to show up with any test cases I've found for the current shuffle lowering, but previous attempts would benefit from this and it seems generally useful. I've tested it directly using intrinsics, which also shows that it will work with hand vectorized code as well. Note that even though pshufd isn't directly used in these tests, it gets exercised because we combine some of the half shuffles into a pshufd first, and then merge them. Differential Revision: http://reviews.llvm.org/D4291 llvm-svn: 211890
This commit is contained in:
Chandler Carruth
parent
c62b16ce89
commit
127f1b532c
@ -19061,6 +19061,88 @@ static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
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}
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}
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/// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
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///
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/// We walk up the chain, skipping shuffles of the other half and looking
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/// through shuffles which switch halves trying to find a shuffle of the same
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/// pair of dwords.
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static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
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SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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assert(
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(N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
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"Called with something other than an x86 128-bit half shuffle!");
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SDLoc DL(N);
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unsigned CombineOpcode = N.getOpcode();
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// Walk up a single-use chain looking for a combinable shuffle.
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SDValue V = N.getOperand(0);
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for (; V.hasOneUse(); V = V.getOperand(0)) {
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switch (V.getOpcode()) {
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default:
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return false; // Nothing combined!
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case ISD::BITCAST:
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// Skip bitcasts as we always know the type for the target specific
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// instructions.
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continue;
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case X86ISD::PSHUFLW:
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case X86ISD::PSHUFHW:
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if (V.getOpcode() == CombineOpcode)
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break;
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// Other-half shuffles are no-ops.
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continue;
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case X86ISD::PSHUFD: {
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// We can only handle pshufd if the half we are combining either stays in
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// its half, or switches to the other half. Bail if one of these isn't
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// true.
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
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int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
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if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
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(VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
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return false;
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// Map the mask through the pshufd and keep walking up the chain.
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for (int i = 0; i < 4; ++i)
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Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
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// Switch halves if the pshufd does.
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CombineOpcode =
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VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
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continue;
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}
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}
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// Break out of the loop if we break out of the switch.
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break;
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}
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if (!V.hasOneUse())
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// We fell out of the loop without finding a viable combining instruction.
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return false;
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// Record the old value to use in RAUW-ing.
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SDValue Old = V;
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// Merge this node's mask and our incoming mask (adjusted to account for all
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// the pshufd instructions encountered).
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
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for (int &M : Mask)
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M = VMask[M];
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V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
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getV4X86ShuffleImm8ForMask(Mask, DAG));
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// Replace N with its operand as we're going to combine that shuffle away.
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DAG.ReplaceAllUsesWith(N, N.getOperand(0));
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// Replace the combinable shuffle with the combined one, updating all users
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// so that we re-evaluate the chain here.
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DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
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return true;
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}
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/// \brief Try to combine x86 target specific shuffles.
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static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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@ -19080,6 +19162,11 @@ static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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return SDValue();
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}
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// Nuke no-op shuffles that show up after combining.
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if (isNoopShuffleMask(Mask))
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return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
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// Look for simplifications involving one or two shuffle instructions.
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SDValue V = N.getOperand(0);
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switch (N.getOpcode()) {
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default:
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@ -19088,6 +19175,9 @@ static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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case X86ISD::PSHUFHW:
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assert(VT == MVT::v8i16);
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if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
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return SDValue(); // We combined away this shuffle, so we're done.
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// See if this reduces to a PSHUFD which is no more expensive and can
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// combine with more operations.
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if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
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49
test/CodeGen/X86/vector-shuffle-combining.ll
Normal file
49
test/CodeGen/X86/vector-shuffle-combining.ll
Normal file
@ -0,0 +1,49 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-SSE2
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
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declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
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define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw1
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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ret <8 x i16> %c
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}
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define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw2
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw3
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; CHECK-SSE2-NEXT: retq
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufhw1
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; CHECK-SSE2-NEXT: retq
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%b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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