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ARM64: make sure first argument to INSERT_SUBVECTOR has right type.

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Again, coalescing and other optimisations swiftly made the MachineInstrs
consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was
produced.

llvm-svn: 205423
This commit is contained in:
Tim Northover 2014-04-02 14:38:58 +00:00
parent 47864f21b8
commit 128b34bf73
2 changed files with 9 additions and 4 deletions
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2
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -5615,7 +5615,7 @@ SDValue ARM64TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
}
MachineSDNode *N =
DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(Op),
Op.getValueType(), DAG.getUNDEF(Op0.getValueType()),
Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
Op0, DAG.getTargetConstant(SubIdx, MVT::i32));
return SDValue(N, 0);
}

11
test/CodeGen/ARM64/simd-scalar-to-vector.ll
View File

@ -1,10 +1,15 @@
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -O0 | FileCheck %s --check-prefix=CHECK-FAST
define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
; CHECK: uaddlv.16b h0, v0
; CHECK: rshrn.8b v0, v0, #4
; CHECK: dup.16b v0, v0[0]
; CHECK: uaddlv.16b h0, v0
; CHECK: rshrn.8b v0, v0, #4
; CHECK: dup.16b v0, v0[0]
; CHECK: ret
; CHECK-FAST: uaddlv.16b
; CHECK-FAST: rshrn.8b
; CHECK-FAST: dup.16b
%tmp = tail call i32 @llvm.arm64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
%tmp1 = trunc i32 %tmp to i16
%tmp2 = insertelement <8 x i16> undef, i16 %tmp1, i32 0