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[RISCV] Add support for the stepvector intrinsic
This adds almost everything required for supporting the new stepvector intrinsic on RVV. It is lowered to the existing VID_VL SDNode. The only exception is a limitation that RV32 cannot yet lower the intrinsic on i64 vectors. This is because the step operand is (currently) required to be at least as large as the vector element type. I will look into patching that out and loosening the requirement to only an integer pointer type. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99594
This commit is contained in:
Fraser Cormack
parent
0a0068af70
commit
12a3af85a6
@ -483,6 +483,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::STEP_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_REVERSE, VT, Custom);
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}
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@ -1808,6 +1809,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerINSERT_SUBVECTOR(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR:
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return lowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::STEP_VECTOR:
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return lowerSTEP_VECTOR(Op, DAG);
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case ISD::VECTOR_REVERSE:
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return lowerVECTOR_REVERSE(Op, DAG);
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case ISD::BUILD_VECTOR:
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@ -3254,6 +3257,17 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
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return DAG.getBitcast(Op.getSimpleValueType(), Slidedown);
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}
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// Implement step_vector to the vid instruction.
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SDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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assert(Op.getConstantOperandAPInt(0) == 1 && "Unexpected step value");
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MVT VT = Op.getSimpleValueType();
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SDValue Mask, VL;
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std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
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return DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL);
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}
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// Implement vector_reverse using vrgather.vv with indices determined by
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// subtracting the id of each element from (VLMAX-1). This will convert
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// the indices like so:
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@ -473,6 +473,7 @@ private:
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SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const;
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183
test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
Normal file
183
test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
Normal file
@ -0,0 +1,183 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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declare <2 x i8> @llvm.experimental.stepvector.v2i8()
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define <2 x i8> @stepvector_v2i8() {
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; CHECK-LABEL: stepvector_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
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ret <2 x i8> %v
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}
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declare <4 x i8> @llvm.experimental.stepvector.v4i8()
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define <4 x i8> @stepvector_v4i8() {
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; CHECK-LABEL: stepvector_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
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ret <4 x i8> %v
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}
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declare <8 x i8> @llvm.experimental.stepvector.v8i8()
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define <8 x i8> @stepvector_v8i8() {
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; CHECK-LABEL: stepvector_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
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ret <8 x i8> %v
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}
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declare <16 x i8> @llvm.experimental.stepvector.v16i8()
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define <16 x i8> @stepvector_v16i8() {
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; CHECK-LABEL: stepvector_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 16, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.experimental.stepvector.v16i8()
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ret <16 x i8> %v
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}
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declare <2 x i16> @llvm.experimental.stepvector.v2i16()
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define <2 x i16> @stepvector_v2i16() {
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; CHECK-LABEL: stepvector_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
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ret <2 x i16> %v
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}
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declare <4 x i16> @llvm.experimental.stepvector.v4i16()
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define <4 x i16> @stepvector_v4i16() {
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; CHECK-LABEL: stepvector_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
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ret <4 x i16> %v
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}
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declare <8 x i16> @llvm.experimental.stepvector.v8i16()
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define <8 x i16> @stepvector_v8i16() {
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; CHECK-LABEL: stepvector_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 8, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i16> @llvm.experimental.stepvector.v8i16()
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ret <8 x i16> %v
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}
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declare <16 x i16> @llvm.experimental.stepvector.v16i16()
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define <16 x i16> @stepvector_v16i16() {
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; LMULMAX1-LABEL: stepvector_v16i16:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI7_0)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI7_0)
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; LMULMAX1-NEXT: vsetivli a1, 8, e16,m1,ta,mu
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; LMULMAX1-NEXT: vle16.v v9, (a0)
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; LMULMAX1-NEXT: vid.v v8
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; LMULMAX1-NEXT: ret
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;
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; LMULMAX2-LABEL: stepvector_v16i16:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli a0, 16, e16,m2,ta,mu
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; LMULMAX2-NEXT: vid.v v8
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; LMULMAX2-NEXT: ret
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%v = call <16 x i16> @llvm.experimental.stepvector.v16i16()
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ret <16 x i16> %v
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}
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declare <2 x i32> @llvm.experimental.stepvector.v2i32()
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define <2 x i32> @stepvector_v2i32() {
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; CHECK-LABEL: stepvector_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
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ret <2 x i32> %v
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}
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declare <4 x i32> @llvm.experimental.stepvector.v4i32()
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define <4 x i32> @stepvector_v4i32() {
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; CHECK-LABEL: stepvector_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e32,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i32> @llvm.experimental.stepvector.v4i32()
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ret <4 x i32> %v
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}
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declare <8 x i32> @llvm.experimental.stepvector.v8i32()
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define <8 x i32> @stepvector_v8i32() {
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; LMULMAX1-LABEL: stepvector_v8i32:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI10_0)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI10_0)
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; LMULMAX1-NEXT: vsetivli a1, 4, e32,m1,ta,mu
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; LMULMAX1-NEXT: vle32.v v9, (a0)
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; LMULMAX1-NEXT: vid.v v8
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; LMULMAX1-NEXT: ret
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;
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; LMULMAX2-LABEL: stepvector_v8i32:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli a0, 8, e32,m2,ta,mu
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; LMULMAX2-NEXT: vid.v v8
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; LMULMAX2-NEXT: ret
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%v = call <8 x i32> @llvm.experimental.stepvector.v8i32()
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ret <8 x i32> %v
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}
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declare <16 x i32> @llvm.experimental.stepvector.v16i32()
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define <16 x i32> @stepvector_v16i32() {
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; LMULMAX1-LABEL: stepvector_v16i32:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_0)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_0)
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; LMULMAX1-NEXT: vsetivli a1, 4, e32,m1,ta,mu
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; LMULMAX1-NEXT: vle32.v v9, (a0)
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_1)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_1)
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; LMULMAX1-NEXT: vle32.v v10, (a0)
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_2)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_2)
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; LMULMAX1-NEXT: vle32.v v11, (a0)
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; LMULMAX1-NEXT: vid.v v8
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; LMULMAX1-NEXT: ret
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;
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; LMULMAX2-LABEL: stepvector_v16i32:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: lui a0, %hi(.LCPI11_0)
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; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI11_0)
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; LMULMAX2-NEXT: vsetivli a1, 8, e32,m2,ta,mu
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; LMULMAX2-NEXT: vle32.v v10, (a0)
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; LMULMAX2-NEXT: vid.v v8
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; LMULMAX2-NEXT: ret
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%v = call <16 x i32> @llvm.experimental.stepvector.v16i32()
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ret <16 x i32> %v
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}
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294
test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
Normal file
294
test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
Normal file
@ -0,0 +1,294 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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declare <2 x i8> @llvm.experimental.stepvector.v2i8()
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define <2 x i8> @stepvector_v2i8() {
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; CHECK-LABEL: stepvector_v2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
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ret <2 x i8> %v
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}
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declare <4 x i8> @llvm.experimental.stepvector.v4i8()
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define <4 x i8> @stepvector_v4i8() {
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; CHECK-LABEL: stepvector_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
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ret <4 x i8> %v
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}
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declare <8 x i8> @llvm.experimental.stepvector.v8i8()
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define <8 x i8> @stepvector_v8i8() {
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; CHECK-LABEL: stepvector_v8i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
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ret <8 x i8> %v
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}
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declare <16 x i8> @llvm.experimental.stepvector.v16i8()
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define <16 x i8> @stepvector_v16i8() {
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; CHECK-LABEL: stepvector_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 16, e8,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <16 x i8> @llvm.experimental.stepvector.v16i8()
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ret <16 x i8> %v
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}
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declare <2 x i16> @llvm.experimental.stepvector.v2i16()
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define <2 x i16> @stepvector_v2i16() {
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; CHECK-LABEL: stepvector_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
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ret <2 x i16> %v
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}
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declare <4 x i16> @llvm.experimental.stepvector.v4i16()
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define <4 x i16> @stepvector_v4i16() {
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; CHECK-LABEL: stepvector_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
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ret <4 x i16> %v
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}
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declare <8 x i16> @llvm.experimental.stepvector.v8i16()
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define <8 x i16> @stepvector_v8i16() {
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; CHECK-LABEL: stepvector_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 8, e16,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <8 x i16> @llvm.experimental.stepvector.v8i16()
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ret <8 x i16> %v
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}
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declare <16 x i16> @llvm.experimental.stepvector.v16i16()
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define <16 x i16> @stepvector_v16i16() {
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; LMULMAX1-LABEL: stepvector_v16i16:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: lui a0, %hi(.LCPI7_0)
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; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI7_0)
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; LMULMAX1-NEXT: vsetivli a1, 8, e16,m1,ta,mu
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; LMULMAX1-NEXT: vle16.v v9, (a0)
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; LMULMAX1-NEXT: vid.v v8
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; LMULMAX1-NEXT: ret
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;
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; LMULMAX2-LABEL: stepvector_v16i16:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli a0, 16, e16,m2,ta,mu
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; LMULMAX2-NEXT: vid.v v8
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; LMULMAX2-NEXT: ret
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%v = call <16 x i16> @llvm.experimental.stepvector.v16i16()
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ret <16 x i16> %v
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}
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declare <2 x i32> @llvm.experimental.stepvector.v2i32()
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define <2 x i32> @stepvector_v2i32() {
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; CHECK-LABEL: stepvector_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: ret
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%v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
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ret <2 x i32> %v
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}
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declare <4 x i32> @llvm.experimental.stepvector.v4i32()
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define <4 x i32> @stepvector_v4i32() {
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; CHECK-LABEL: stepvector_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a0, 4, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <4 x i32> @llvm.experimental.stepvector.v4i32()
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.experimental.stepvector.v8i32()
|
||||
|
||||
define <8 x i32> @stepvector_v8i32() {
|
||||
; LMULMAX1-LABEL: stepvector_v8i32:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: lui a0, %hi(.LCPI10_0)
|
||||
; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI10_0)
|
||||
; LMULMAX1-NEXT: vsetivli a1, 4, e32,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle32.v v9, (a0)
|
||||
; LMULMAX1-NEXT: vid.v v8
|
||||
; LMULMAX1-NEXT: ret
|
||||
;
|
||||
; LMULMAX2-LABEL: stepvector_v8i32:
|
||||
; LMULMAX2: # %bb.0:
|
||||
; LMULMAX2-NEXT: vsetivli a0, 8, e32,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vid.v v8
|
||||
; LMULMAX2-NEXT: ret
|
||||
%v = call <8 x i32> @llvm.experimental.stepvector.v8i32()
|
||||
ret <8 x i32> %v
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.experimental.stepvector.v16i32()
|
||||
|
||||
define <16 x i32> @stepvector_v16i32() {
|
||||
; LMULMAX1-LABEL: stepvector_v16i32:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_0)
|
||||
; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_0)
|
||||
; LMULMAX1-NEXT: vsetivli a1, 4, e32,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vle32.v v9, (a0)
|
||||
; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_1)
|
||||
; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_1)
|
||||
; LMULMAX1-NEXT: vle32.v v10, (a0)
|
||||
; LMULMAX1-NEXT: lui a0, %hi(.LCPI11_2)
|
||||
; LMULMAX1-NEXT: addi a0, a0, %lo(.LCPI11_2)
|
||||
; LMULMAX1-NEXT: vle32.v v11, (a0)
|
||||
; LMULMAX1-NEXT: vid.v v8
|
||||
; LMULMAX1-NEXT: ret
|
||||
;
|
||||
; LMULMAX2-LABEL: stepvector_v16i32:
|
||||
; LMULMAX2: # %bb.0:
|
||||
; LMULMAX2-NEXT: lui a0, %hi(.LCPI11_0)
|
||||
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI11_0)
|
||||
; LMULMAX2-NEXT: vsetivli a1, 8, e32,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vle32.v v10, (a0)
|
||||
; LMULMAX2-NEXT: vid.v v8
|
||||
; LMULMAX2-NEXT: ret
|
||||
%v = call <16 x i32> @llvm.experimental.stepvector.v16i32()
|
||||
ret <16 x i32> %v
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.experimental.stepvector.v2i64()
|
||||
|
||||
define <2 x i64> @stepvector_v2i64() {
|
||||
; CHECK-LABEL: stepvector_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetivli a0, 2, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <2 x i64> @llvm.experimental.stepvector.v2i64()
|
||||
ret <2 x i64> %v
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.experimental.stepvector.v4i64()
|
||||
|
||||
define <4 x i64> @stepvector_v4i64() {
|
||||
; LMULMAX1-LABEL: stepvector_v4i64:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a0, zero, 2
|
||||
; LMULMAX1-NEXT: vsetivli a1, 2, e64,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vmv.v.i v9, 3
|
||||
; LMULMAX1-NEXT: vmv.s.x v9, a0
|
||||
; LMULMAX1-NEXT: vid.v v8
|
||||
; LMULMAX1-NEXT: ret
|
||||
;
|
||||
; LMULMAX2-LABEL: stepvector_v4i64:
|
||||
; LMULMAX2: # %bb.0:
|
||||
; LMULMAX2-NEXT: vsetivli a0, 4, e64,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vid.v v8
|
||||
; LMULMAX2-NEXT: ret
|
||||
%v = call <4 x i64> @llvm.experimental.stepvector.v4i64()
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.experimental.stepvector.v8i64()
|
||||
|
||||
define <8 x i64> @stepvector_v8i64() {
|
||||
; LMULMAX1-LABEL: stepvector_v8i64:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a0, zero, 2
|
||||
; LMULMAX1-NEXT: vsetivli a1, 2, e64,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vmv.v.i v10, 5
|
||||
; LMULMAX1-NEXT: addi a1, zero, 4
|
||||
; LMULMAX1-NEXT: vmv.s.x v10, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v11, 7
|
||||
; LMULMAX1-NEXT: addi a1, zero, 6
|
||||
; LMULMAX1-NEXT: vmv.s.x v11, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v9, 3
|
||||
; LMULMAX1-NEXT: vmv.s.x v9, a0
|
||||
; LMULMAX1-NEXT: vid.v v8
|
||||
; LMULMAX1-NEXT: ret
|
||||
;
|
||||
; LMULMAX2-LABEL: stepvector_v8i64:
|
||||
; LMULMAX2: # %bb.0:
|
||||
; LMULMAX2-NEXT: lui a0, %hi(.LCPI14_0)
|
||||
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI14_0)
|
||||
; LMULMAX2-NEXT: vsetivli a1, 4, e64,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vle64.v v10, (a0)
|
||||
; LMULMAX2-NEXT: vid.v v8
|
||||
; LMULMAX2-NEXT: ret
|
||||
%v = call <8 x i64> @llvm.experimental.stepvector.v8i64()
|
||||
ret <8 x i64> %v
|
||||
}
|
||||
|
||||
declare <16 x i64> @llvm.experimental.stepvector.v16i64()
|
||||
|
||||
define <16 x i64> @stepvector_v16i64() {
|
||||
; LMULMAX1-LABEL: stepvector_v16i64:
|
||||
; LMULMAX1: # %bb.0:
|
||||
; LMULMAX1-NEXT: addi a0, zero, 2
|
||||
; LMULMAX1-NEXT: vsetivli a1, 2, e64,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vmv.v.i v10, 5
|
||||
; LMULMAX1-NEXT: addi a1, zero, 4
|
||||
; LMULMAX1-NEXT: vmv.s.x v10, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v11, 7
|
||||
; LMULMAX1-NEXT: addi a1, zero, 6
|
||||
; LMULMAX1-NEXT: vmv.s.x v11, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v12, 9
|
||||
; LMULMAX1-NEXT: addi a1, zero, 8
|
||||
; LMULMAX1-NEXT: vmv.s.x v12, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v13, 11
|
||||
; LMULMAX1-NEXT: addi a1, zero, 10
|
||||
; LMULMAX1-NEXT: vmv.s.x v13, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v14, 13
|
||||
; LMULMAX1-NEXT: addi a1, zero, 12
|
||||
; LMULMAX1-NEXT: vmv.s.x v14, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v15, 15
|
||||
; LMULMAX1-NEXT: addi a1, zero, 14
|
||||
; LMULMAX1-NEXT: vmv.s.x v15, a1
|
||||
; LMULMAX1-NEXT: vmv.v.i v9, 3
|
||||
; LMULMAX1-NEXT: vmv.s.x v9, a0
|
||||
; LMULMAX1-NEXT: vid.v v8
|
||||
; LMULMAX1-NEXT: ret
|
||||
;
|
||||
; LMULMAX2-LABEL: stepvector_v16i64:
|
||||
; LMULMAX2: # %bb.0:
|
||||
; LMULMAX2-NEXT: lui a0, %hi(.LCPI15_0)
|
||||
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI15_0)
|
||||
; LMULMAX2-NEXT: vsetivli a1, 4, e64,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vle64.v v10, (a0)
|
||||
; LMULMAX2-NEXT: lui a0, %hi(.LCPI15_1)
|
||||
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI15_1)
|
||||
; LMULMAX2-NEXT: vle64.v v12, (a0)
|
||||
; LMULMAX2-NEXT: lui a0, %hi(.LCPI15_2)
|
||||
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI15_2)
|
||||
; LMULMAX2-NEXT: vle64.v v14, (a0)
|
||||
; LMULMAX2-NEXT: vid.v v8
|
||||
; LMULMAX2-NEXT: ret
|
||||
%v = call <16 x i64> @llvm.experimental.stepvector.v16i64()
|
||||
ret <16 x i64> %v
|
||||
}
|
||||
233
test/CodeGen/RISCV/rvv/stepvector-rv32.ll
Normal file
233
test/CodeGen/RISCV/rvv/stepvector-rv32.ll
Normal file
@ -0,0 +1,233 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
|
||||
|
||||
define <vscale x 1 x i8> @stepvector_nxv1i8() {
|
||||
; CHECK-LABEL: stepvector_nxv1i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
|
||||
ret <vscale x 1 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
|
||||
|
||||
define <vscale x 2 x i8> @stepvector_nxv2i8() {
|
||||
; CHECK-LABEL: stepvector_nxv2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
|
||||
|
||||
define <vscale x 4 x i8> @stepvector_nxv4i8() {
|
||||
; CHECK-LABEL: stepvector_nxv4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
|
||||
ret <vscale x 4 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
|
||||
|
||||
define <vscale x 8 x i8> @stepvector_nxv8i8() {
|
||||
; CHECK-LABEL: stepvector_nxv8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
|
||||
ret <vscale x 8 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
|
||||
|
||||
define <vscale x 16 x i8> @stepvector_nxv16i8() {
|
||||
; CHECK-LABEL: stepvector_nxv16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
|
||||
ret <vscale x 16 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
|
||||
|
||||
define <vscale x 32 x i8> @stepvector_nxv32i8() {
|
||||
; CHECK-LABEL: stepvector_nxv32i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
|
||||
ret <vscale x 32 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
|
||||
|
||||
define <vscale x 64 x i8> @stepvector_nxv64i8() {
|
||||
; CHECK-LABEL: stepvector_nxv64i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
|
||||
ret <vscale x 64 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
|
||||
|
||||
define <vscale x 1 x i16> @stepvector_nxv1i16() {
|
||||
; CHECK-LABEL: stepvector_nxv1i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
|
||||
ret <vscale x 1 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
|
||||
|
||||
define <vscale x 2 x i16> @stepvector_nxv2i16() {
|
||||
; CHECK-LABEL: stepvector_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
|
||||
|
||||
define <vscale x 4 x i16> @stepvector_nxv4i16() {
|
||||
; CHECK-LABEL: stepvector_nxv4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
|
||||
ret <vscale x 4 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
|
||||
|
||||
define <vscale x 8 x i16> @stepvector_nxv8i16() {
|
||||
; CHECK-LABEL: stepvector_nxv8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
|
||||
ret <vscale x 8 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
|
||||
|
||||
define <vscale x 16 x i16> @stepvector_nxv16i16() {
|
||||
; CHECK-LABEL: stepvector_nxv16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
|
||||
ret <vscale x 16 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
|
||||
|
||||
define <vscale x 32 x i16> @stepvector_nxv32i16() {
|
||||
; CHECK-LABEL: stepvector_nxv32i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
|
||||
ret <vscale x 32 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
|
||||
|
||||
define <vscale x 1 x i32> @stepvector_nxv1i32() {
|
||||
; CHECK-LABEL: stepvector_nxv1i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
|
||||
ret <vscale x 1 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
|
||||
|
||||
define <vscale x 2 x i32> @stepvector_nxv2i32() {
|
||||
; CHECK-LABEL: stepvector_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||
|
||||
define <vscale x 4 x i32> @stepvector_nxv4i32() {
|
||||
; CHECK-LABEL: stepvector_nxv4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||
ret <vscale x 4 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
|
||||
|
||||
define <vscale x 8 x i32> @stepvector_nxv8i32() {
|
||||
; CHECK-LABEL: stepvector_nxv8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
|
||||
|
||||
define <vscale x 16 x i32> @stepvector_nxv16i32() {
|
||||
; CHECK-LABEL: stepvector_nxv16i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 32 x i32> @llvm.experimental.stepvector.nxv32i32()
|
||||
|
||||
define <vscale x 32 x i32> @stepvector_nxv32i32() {
|
||||
; CHECK-LABEL: stepvector_nxv32i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: slli a0, a0, 1
|
||||
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: vadd.vx v16, v8, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 32 x i32> @llvm.experimental.stepvector.nxv32i32()
|
||||
ret <vscale x 32 x i32> %v
|
||||
}
|
||||
280
test/CodeGen/RISCV/rvv/stepvector-rv64.ll
Normal file
280
test/CodeGen/RISCV/rvv/stepvector-rv64.ll
Normal file
@ -0,0 +1,280 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
|
||||
|
||||
define <vscale x 1 x i8> @stepvector_nxv1i8() {
|
||||
; CHECK-LABEL: stepvector_nxv1i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8()
|
||||
ret <vscale x 1 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
|
||||
|
||||
define <vscale x 2 x i8> @stepvector_nxv2i8() {
|
||||
; CHECK-LABEL: stepvector_nxv2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8()
|
||||
ret <vscale x 2 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
|
||||
|
||||
define <vscale x 4 x i8> @stepvector_nxv4i8() {
|
||||
; CHECK-LABEL: stepvector_nxv4i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8()
|
||||
ret <vscale x 4 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
|
||||
|
||||
define <vscale x 8 x i8> @stepvector_nxv8i8() {
|
||||
; CHECK-LABEL: stepvector_nxv8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
|
||||
ret <vscale x 8 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
|
||||
|
||||
define <vscale x 16 x i8> @stepvector_nxv16i8() {
|
||||
; CHECK-LABEL: stepvector_nxv16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
|
||||
ret <vscale x 16 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
|
||||
|
||||
define <vscale x 32 x i8> @stepvector_nxv32i8() {
|
||||
; CHECK-LABEL: stepvector_nxv32i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8()
|
||||
ret <vscale x 32 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
|
||||
|
||||
define <vscale x 64 x i8> @stepvector_nxv64i8() {
|
||||
; CHECK-LABEL: stepvector_nxv64i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8()
|
||||
ret <vscale x 64 x i8> %v
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
|
||||
|
||||
define <vscale x 1 x i16> @stepvector_nxv1i16() {
|
||||
; CHECK-LABEL: stepvector_nxv1i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
|
||||
ret <vscale x 1 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
|
||||
|
||||
define <vscale x 2 x i16> @stepvector_nxv2i16() {
|
||||
; CHECK-LABEL: stepvector_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16()
|
||||
ret <vscale x 2 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
|
||||
|
||||
define <vscale x 4 x i16> @stepvector_nxv4i16() {
|
||||
; CHECK-LABEL: stepvector_nxv4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
|
||||
ret <vscale x 4 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
|
||||
|
||||
define <vscale x 8 x i16> @stepvector_nxv8i16() {
|
||||
; CHECK-LABEL: stepvector_nxv8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
|
||||
ret <vscale x 8 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
|
||||
|
||||
define <vscale x 16 x i16> @stepvector_nxv16i16() {
|
||||
; CHECK-LABEL: stepvector_nxv16i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16()
|
||||
ret <vscale x 16 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
|
||||
|
||||
define <vscale x 32 x i16> @stepvector_nxv32i16() {
|
||||
; CHECK-LABEL: stepvector_nxv32i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16()
|
||||
ret <vscale x 32 x i16> %v
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
|
||||
|
||||
define <vscale x 1 x i32> @stepvector_nxv1i32() {
|
||||
; CHECK-LABEL: stepvector_nxv1i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32()
|
||||
ret <vscale x 1 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
|
||||
|
||||
define <vscale x 2 x i32> @stepvector_nxv2i32() {
|
||||
; CHECK-LABEL: stepvector_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||
|
||||
define <vscale x 4 x i32> @stepvector_nxv4i32() {
|
||||
; CHECK-LABEL: stepvector_nxv4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
|
||||
ret <vscale x 4 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
|
||||
|
||||
define <vscale x 8 x i32> @stepvector_nxv8i32() {
|
||||
; CHECK-LABEL: stepvector_nxv8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32()
|
||||
ret <vscale x 8 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
|
||||
|
||||
define <vscale x 16 x i32> @stepvector_nxv16i32() {
|
||||
; CHECK-LABEL: stepvector_nxv16i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
|
||||
ret <vscale x 16 x i32> %v
|
||||
}
|
||||
|
||||
declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
|
||||
|
||||
define <vscale x 1 x i64> @stepvector_nxv1i64() {
|
||||
; CHECK-LABEL: stepvector_nxv1i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
|
||||
ret <vscale x 1 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
|
||||
|
||||
define <vscale x 2 x i64> @stepvector_nxv2i64() {
|
||||
; CHECK-LABEL: stepvector_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
|
||||
|
||||
define <vscale x 4 x i64> @stepvector_nxv4i64() {
|
||||
; CHECK-LABEL: stepvector_nxv4i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
|
||||
ret <vscale x 4 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
|
||||
|
||||
define <vscale x 8 x i64> @stepvector_nxv8i64() {
|
||||
; CHECK-LABEL: stepvector_nxv8i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64()
|
||||
ret <vscale x 8 x i64> %v
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
||||
|
||||
define <vscale x 16 x i64> @stepvector_nxv16i64() {
|
||||
; CHECK-LABEL: stepvector_nxv16i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
|
||||
; CHECK-NEXT: vid.v v8
|
||||
; CHECK-NEXT: vadd.vx v16, v8, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
|
||||
ret <vscale x 16 x i64> %v
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user