RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

Add MULHU and MULHS nodes for the high part of an (un)signed 32x32=64b

Browse Source 
multiply.

llvm-svn: 21102
This commit is contained in:
Nate Begeman 2005-04-05 22:36:56 +00:00
parent 613a940af8
commit 12af81407b
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -90,7 +90,7 @@ namespace ISD {
// Simple binary arithmetic operators. // Simple binary arithmetic operators.
ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, ADD, SUB, MUL, MULHU, MULHS, SDIV, UDIV, SREM, UREM,
// Bitwise operators. // Bitwise operators.
AND, OR, XOR, SHL, SRA, SRL, AND, OR, XOR, SHL, SRA, SRL,

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1130,6 +1130,8 @@ const char *SDNode::getOperationName() const {
case ISD::ADD: return "add"; case ISD::ADD: return "add";
case ISD::SUB: return "sub"; case ISD::SUB: return "sub";
case ISD::MUL: return "mul"; case ISD::MUL: return "mul";
case ISD::MULHU: return "mulhu";
case ISD::MULHS: return "mulhs";
case ISD::SDIV: return "sdiv"; case ISD::SDIV: return "sdiv";
case ISD::UDIV: return "udiv"; case ISD::UDIV: return "udiv";
case ISD::SREM: return "srem"; case ISD::SREM: return "srem";