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Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.

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llvm-svn: 37643
This commit is contained in:
Evan Cheng 2007-06-19 01:26:51 +00:00
parent 4358a7f1e9
commit 12b3002673
9 changed files with 13 additions and 33 deletions
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4
lib/CodeGen/IfConversion.cpp
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@ -547,10 +547,10 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
bool SeenCondBr = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
if (!BBI.CannotBeCopied && !TII->CanBeDuplicated(I))
const TargetInstrDescriptor *TID = I->getInstrDescriptor();
if ((TID->Flags & M_NOT_DUPLICABLE) != 0)
BBI.CannotBeCopied = true;
const TargetInstrDescriptor *TID = I->getInstrDescriptor();
bool isPredicated = TII->isPredicated(I);
bool isCondBr = BBI.IsBrAnalyzable &&
(TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0;

29
lib/Target/ARM/ARMInstrInfo.cpp
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@ -446,35 +446,6 @@ bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
}
bool ARMInstrInfo::CanBeDuplicated(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: return true;
// These have unique labels.
case ARM::PICADD:
case ARM::PICLD:
case ARM::PICLDZH:
case ARM::PICLDZB:
case ARM::PICLDH:
case ARM::PICLDB:
case ARM::PICLDSH:
case ARM::PICLDSB:
case ARM::PICSTR:
case ARM::PICSTRH:
case ARM::PICSTRB:
case ARM::LEApcrel:
case ARM::LEApcrelJT:
case ARM::tPICADD:
case ARM::tLEApcrel:
case ARM::tLEApcrelJT:
case ARM::CONSTPOOL_ENTRY:
// These embed jumptables.
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
return false;
}
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode();

2
lib/Target/ARM/ARMInstrInfo.h
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@ -106,8 +106,6 @@ public:
// Predication support.
virtual bool isPredicated(const MachineInstr *MI) const;
virtual bool CanBeDuplicated(const MachineInstr *MI) const;
virtual
bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const;

6
lib/Target/ARM/ARMInstrInfo.td
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@ -533,6 +533,7 @@ PseudoInst<(ops GPR:$rD, pred:$p),
/// the function. The first operand is the ID# for this instruction, the second
/// is the index into the MachineConstantPool that this is, the third is the
/// size in bytes of this constant pool entry.
let isNotDuplicable = 1 in
def CONSTPOOL_ENTRY :
PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
"${instid:label} ${cpidx:cpentry}", []>;
@ -552,6 +553,7 @@ PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
let isNotDuplicable = 1 in {
def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p),
"$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
@ -598,6 +600,7 @@ def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
}
}
//===----------------------------------------------------------------------===//
// Control Flow Instructions.
@ -637,6 +640,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
def B : AXI<(ops brtarget:$dst), "b $dst",
[(br bb:$dst)]>;
let isNotDuplicable = 1 in {
def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
"mov pc, $dst \n$jt",
[(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
@ -649,6 +653,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
[(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
imm:$id)]>;
}
}
def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
[(ARMbrcond bb:$dst, imm:$cc)]>;
@ -1152,6 +1157,7 @@ def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
[]>;
//===----------------------------------------------------------------------===//
// TLS Instructions
//

1
lib/Target/ARM/ARMInstrThumb.td
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@ -170,6 +170,7 @@ PseudoInst<(ops i32imm:$amt),
"@ tADJCALLSTACKDOWN $amt",
[(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
let isNotDuplicable = 1 in
def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
"$cp:\n\tadd $dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;

1
lib/Target/Target.td
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@ -193,6 +193,7 @@ class Instruction {
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit noResults = 0; // Does this instruction produce no results?
bit clobbersPred = 0; // Does it clobbers condition code / predicate?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.

1
utils/TableGen/CodeGenInstruction.h
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@ -98,6 +98,7 @@ namespace llvm {
bool hasCtrlDep;
bool noResults;
bool clobbersPred;
bool isNotDuplicable;
/// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
/// where $foo is a whole operand and $foo.bar refers to a suboperand.

1
utils/TableGen/CodeGenTarget.cpp
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@ -371,6 +371,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
hasCtrlDep = R->getValueAsBit("hasCtrlDep");
noResults = R->getValueAsBit("noResults");
clobbersPred = R->getValueAsBit("clobbersPred");
isNotDuplicable = R->getValueAsBit("isNotDuplicable");
hasVariableNumberOfOperands = false;
DagInit *DI;

1
utils/TableGen/InstrInfoEmitter.cpp
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@ -242,6 +242,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
if (Inst.clobbersPred) OS << "|M_CLOBBERS_PRED";
if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
if (Inst.hasVariableNumberOfOperands)