mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
Add an option and stuff implementation of a dag isel emitter
llvm-svn: 23236
This commit is contained in:
parent
29929a3745
commit
12c57505bf
38
utils/TableGen/DAGISelEmitter.h
Normal file
38
utils/TableGen/DAGISelEmitter.h
Normal file
@ -0,0 +1,38 @@
|
||||
//===- DAGISelEmitter.h - Generate an instruction selector ------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by Chris Lattner and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This tablegen backend emits a DAG instruction selector.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef DAGISEL_EMITTER_H
|
||||
#define DAGISEL_EMITTER_H
|
||||
|
||||
#include "TableGenBackend.h"
|
||||
#include "CodeGenTarget.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// InstrSelectorEmitter - The top-level class which coordinates construction
|
||||
/// and emission of the instruction selector.
|
||||
///
|
||||
class DAGISelEmitter : public TableGenBackend {
|
||||
RecordKeeper &Records;
|
||||
CodeGenTarget Target;
|
||||
|
||||
public:
|
||||
DAGISelEmitter(RecordKeeper &R) : Records(R) {}
|
||||
|
||||
// run - Output the isel, returning true on failure.
|
||||
void run(std::ostream &OS) {}
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
@ -24,6 +24,7 @@
|
||||
#include "InstrInfoEmitter.h"
|
||||
#include "AsmWriterEmitter.h"
|
||||
#include "InstrSelectorEmitter.h"
|
||||
#include "DAGISelEmitter.h"
|
||||
#include <algorithm>
|
||||
#include <cstdio>
|
||||
#include <fstream>
|
||||
@ -34,6 +35,7 @@ enum ActionType {
|
||||
GenEmitter,
|
||||
GenRegisterEnums, GenRegister, GenRegisterHeader,
|
||||
GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
|
||||
GenDAGISel,
|
||||
PrintEnums,
|
||||
Parse
|
||||
};
|
||||
@ -59,6 +61,8 @@ namespace {
|
||||
"Generate assembly writer"),
|
||||
clEnumValN(GenInstrSelector, "gen-instr-selector",
|
||||
"Generate an instruction selector"),
|
||||
clEnumValN(GenDAGISel, "gen-dag-isel",
|
||||
"Generate a DAG instruction selector"),
|
||||
clEnumValN(PrintEnums, "print-enums",
|
||||
"Print enum values for a class"),
|
||||
clEnumValN(Parse, "parse",
|
||||
@ -465,6 +469,9 @@ int main(int argc, char **argv) {
|
||||
case GenInstrSelector:
|
||||
InstrSelectorEmitter(Records).run(*Out);
|
||||
break;
|
||||
case GenDAGISel:
|
||||
DAGISelEmitter(Records).run(*Out);
|
||||
break;
|
||||
case PrintEnums:
|
||||
{
|
||||
std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
|
||||
|
Loading…
Reference in New Issue
Block a user