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[Intrinsic] Expand SMULFIX to MUL, MULH[US], or [US]MUL_LOHI on vector arguments
r zero scale SMULFIX, expand into MUL which produces better code for X86. For vector arguments, expand into MUL if SMULFIX is provided with a zero scale. Otherwise, expand into MULH[US] or [US]MUL_LOHI. Differential Revision: https://reviews.llvm.org/D56987 llvm-svn: 352783
This commit is contained in:
Leonard Chan
parent
9394787051
commit
12cd3e33d7
@ -141,6 +141,7 @@ class VectorLegalizer {
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SDValue ExpandROT(SDValue Op);
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SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
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SDValue ExpandAddSubSat(SDValue Op);
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SDValue ExpandFixedPointMul(SDValue Op);
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SDValue ExpandStrictFPOp(SDValue Op);
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/// Implements vector promotion.
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@ -782,6 +783,8 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
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case ISD::UADDSAT:
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case ISD::SADDSAT:
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return ExpandAddSubSat(Op);
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case ISD::SMULFIX:
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return ExpandFixedPointMul(Op);
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case ISD::STRICT_FADD:
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case ISD::STRICT_FSUB:
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case ISD::STRICT_FMUL:
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@ -1217,6 +1220,12 @@ SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
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return DAG.UnrollVectorOp(Op.getNode());
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}
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SDValue VectorLegalizer::ExpandFixedPointMul(SDValue Op) {
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if (SDValue Expanded = TLI.expandFixedPointMul(Op.getNode(), DAG))
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return Expanded;
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return DAG.UnrollVectorOp(Op.getNode());
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}
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SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
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EVT VT = Op.getValueType();
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EVT EltVT = VT.getVectorElementType();
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@ -5362,29 +5362,25 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
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SDValue
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TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
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assert(Node->getOpcode() == ISD::SMULFIX && "Expected opcode to be SMULFIX.");
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assert(Node->getNumOperands() == 3 &&
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"Expected signed fixed point multiplication to have 3 operands.");
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SDLoc dl(Node);
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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assert(LHS.getValueType().isScalarInteger() &&
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"Expected operands to be integers. Vector of int arguments should "
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"already be unrolled.");
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assert(RHS.getValueType().isScalarInteger() &&
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"Expected operands to be integers. Vector of int arguments should "
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"already be unrolled.");
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EVT VT = LHS.getValueType();
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unsigned Scale = Node->getConstantOperandVal(2);
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// [us]mul.fix(a, b, 0) -> mul(a, b)
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if (!Scale) {
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if (VT.isVector() && !isOperationLegalOrCustom(ISD::MUL, VT))
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return SDValue();
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return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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}
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assert(LHS.getValueType() == RHS.getValueType() &&
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"Expected both operands to be the same type");
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unsigned Scale = Node->getConstantOperandVal(2);
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EVT VT = LHS.getValueType();
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assert(Scale < VT.getScalarSizeInBits() &&
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"Expected scale to be less than the number of bits.");
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if (!Scale)
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return DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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// Get the upper and lower bits of the result.
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SDValue Lo, Hi;
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if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
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@ -5395,6 +5391,8 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
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} else if (isOperationLegalOrCustom(ISD::MULHS, VT)) {
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Lo = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
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Hi = DAG.getNode(ISD::MULHS, dl, VT, LHS, RHS);
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} else if (VT.isVector()) {
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return SDValue();
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} else {
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report_fatal_error("Unable to expand signed fixed point multiplication.");
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}
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@ -135,52 +135,27 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; X64-LABEL: vec:
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; X64: # %bb.0:
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
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; X64-NEXT: movd %xmm2, %eax
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; X64-NEXT: cltq
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; X64-NEXT: movd %xmm2, %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: imulq %rax, %rcx
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: shldl $30, %ecx, %eax
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; X64-NEXT: movd %eax, %xmm2
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; X64-NEXT: movd %xmm3, %eax
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; X64-NEXT: cltq
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
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; X64-NEXT: movd %xmm3, %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: imulq %rax, %rcx
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: shldl $30, %ecx, %eax
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; X64-NEXT: movd %eax, %xmm3
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; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; X64-NEXT: movd %xmm1, %eax
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; X64-NEXT: cltq
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; X64-NEXT: movd %xmm0, %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: imulq %rax, %rcx
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: shldl $30, %ecx, %eax
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; X64-NEXT: movd %eax, %xmm2
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X64-NEXT: movd %xmm1, %eax
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; X64-NEXT: cltq
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X64-NEXT: movd %xmm0, %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: imulq %rax, %rcx
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; X64-NEXT: movq %rcx, %rax
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: shldl $30, %ecx, %eax
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; X64-NEXT: movd %eax, %xmm0
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; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; X64-NEXT: movdqa %xmm2, %xmm0
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; X64-NEXT: pxor %xmm2, %xmm2
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; X64-NEXT: pxor %xmm3, %xmm3
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; X64-NEXT: pcmpgtd %xmm1, %xmm3
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; X64-NEXT: pand %xmm0, %xmm3
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; X64-NEXT: pcmpgtd %xmm0, %xmm2
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; X64-NEXT: pand %xmm1, %xmm2
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; X64-NEXT: paddd %xmm3, %xmm2
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
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; X64-NEXT: pmuludq %xmm1, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,3,2,3]
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X64-NEXT: pmuludq %xmm3, %xmm1
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
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; X64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
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; X64-NEXT: psubd %xmm2, %xmm4
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; X64-NEXT: pslld $30, %xmm4
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X64-NEXT: psrld $2, %xmm0
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; X64-NEXT: por %xmm4, %xmm0
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; X64-NEXT: retq
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;
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; X86-LABEL: vec:
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@ -295,32 +270,13 @@ define i4 @func6(i4 %x, i4 %y) nounwind {
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define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
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; X64-LABEL: vec2:
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; X64: # %bb.0:
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
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; X64-NEXT: movd %xmm2, %eax
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
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; X64-NEXT: movd %xmm2, %ecx
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; X64-NEXT: imull %eax, %ecx
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; X64-NEXT: movd %ecx, %xmm2
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
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; X64-NEXT: movd %xmm3, %eax
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; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
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; X64-NEXT: movd %xmm3, %ecx
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; X64-NEXT: imull %eax, %ecx
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; X64-NEXT: movd %ecx, %xmm3
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; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; X64-NEXT: movd %xmm1, %eax
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; X64-NEXT: movd %xmm0, %ecx
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; X64-NEXT: imull %eax, %ecx
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; X64-NEXT: movd %ecx, %xmm2
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X64-NEXT: movd %xmm1, %eax
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X64-NEXT: movd %xmm0, %ecx
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; X64-NEXT: imull %eax, %ecx
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; X64-NEXT: movd %ecx, %xmm0
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; X64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; X64-NEXT: movdqa %xmm2, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; X64-NEXT: pmuludq %xmm1, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X64-NEXT: pmuludq %xmm2, %xmm1
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X64-NEXT: retq
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;
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; X86-LABEL: vec2:
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