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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D41663 llvm-svn: 323908
This commit is contained in:
Marek Olsak
parent
2608200700
commit
1325dff7c0
@ -238,6 +238,26 @@ def int_amdgcn_cvt_pkrtz : Intrinsic<
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[IntrNoMem, IntrSpeculatable]
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>;
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def int_amdgcn_cvt_pknorm_i16 : Intrinsic<
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[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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def int_amdgcn_cvt_pknorm_u16 : Intrinsic<
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[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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def int_amdgcn_cvt_pk_i16 : Intrinsic<
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[llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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def int_amdgcn_cvt_pk_u16 : Intrinsic<
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[llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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def int_amdgcn_class : Intrinsic<
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[llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]
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@ -3957,6 +3957,10 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(CVT_F32_UBYTE2)
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NODE_NAME_CASE(CVT_F32_UBYTE3)
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NODE_NAME_CASE(CVT_PKRTZ_F16_F32)
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NODE_NAME_CASE(CVT_PKNORM_I16_F32)
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NODE_NAME_CASE(CVT_PKNORM_U16_F32)
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NODE_NAME_CASE(CVT_PK_I16_I32)
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NODE_NAME_CASE(CVT_PK_U16_U32)
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NODE_NAME_CASE(FP_TO_FP16)
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NODE_NAME_CASE(FP16_ZEXT)
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NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
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@ -417,6 +417,10 @@ enum NodeType : unsigned {
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// Convert two float 32 numbers into a single register holding two packed f16
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// with round to zero.
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CVT_PKRTZ_F16_F32,
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CVT_PKNORM_I16_F32,
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CVT_PKNORM_U16_F32,
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CVT_PK_I16_I32,
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CVT_PK_U16_U32,
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// Same as the standard node, except the high bits of the resulting integer
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// are known 0.
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@ -35,6 +35,10 @@ def AMDGPUFPPackOp : SDTypeProfile<1, 2,
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[SDTCisFP<1>, SDTCisSameAs<1, 2>]
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>;
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def AMDGPUIntPackOp : SDTypeProfile<1, 2,
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[SDTCisInt<1>, SDTCisSameAs<1, 2>]
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>;
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def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
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[SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
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>;
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@ -142,6 +146,10 @@ def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
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def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
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def AMDGPUpkrtz_f16_f32 : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
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def AMDGPUpknorm_i16_f32 : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
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def AMDGPUpknorm_u16_f32 : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
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def AMDGPUpk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
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def AMDGPUpk_u16_u32 : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
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def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
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@ -205,6 +205,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
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@ -3870,7 +3871,8 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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if (IID == Intrinsic::amdgcn_cvt_pkrtz) {
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switch (IID) {
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case Intrinsic::amdgcn_cvt_pkrtz: {
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SDValue Src0 = N->getOperand(1);
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SDValue Src1 = N->getOperand(2);
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SDLoc SL(N);
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@ -3879,6 +3881,29 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
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return;
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}
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case Intrinsic::amdgcn_cvt_pknorm_i16:
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case Intrinsic::amdgcn_cvt_pknorm_u16:
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case Intrinsic::amdgcn_cvt_pk_i16:
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case Intrinsic::amdgcn_cvt_pk_u16: {
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SDValue Src0 = N->getOperand(1);
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SDValue Src1 = N->getOperand(2);
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SDLoc SL(N);
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unsigned Opcode;
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if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
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Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
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else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
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Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
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else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
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Opcode = AMDGPUISD::CVT_PK_I16_I32;
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else
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Opcode = AMDGPUISD::CVT_PK_U16_U32;
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SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
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Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
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return;
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}
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}
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break;
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}
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case ISD::INTRINSIC_W_CHAIN: {
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@ -4787,10 +4812,27 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::amdgcn_ubfe:
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return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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case Intrinsic::amdgcn_cvt_pkrtz: {
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// FIXME: Stop adding cast if v2f16 legal.
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case Intrinsic::amdgcn_cvt_pkrtz:
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case Intrinsic::amdgcn_cvt_pknorm_i16:
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case Intrinsic::amdgcn_cvt_pknorm_u16:
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case Intrinsic::amdgcn_cvt_pk_i16:
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case Intrinsic::amdgcn_cvt_pk_u16: {
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// FIXME: Stop adding cast if v2f16/v2i16 are legal.
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EVT VT = Op.getValueType();
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SDValue Node = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, DL, MVT::i32,
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unsigned Opcode;
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if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
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Opcode = AMDGPUISD::CVT_PKRTZ_F16_F32;
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else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
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Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
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else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
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Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
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else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
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Opcode = AMDGPUISD::CVT_PK_I16_I32;
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else
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Opcode = AMDGPUISD::CVT_PK_U16_U32;
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SDValue Node = DAG.getNode(Opcode, DL, MVT::i32,
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Op.getOperand(1), Op.getOperand(2));
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return DAG.getNode(ISD::BITCAST, DL, VT, Node);
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}
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@ -408,11 +408,11 @@ defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32
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defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
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defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
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defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
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defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_I32_F32_F32>>;
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defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_I32_F32_F32>>;
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defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpknorm_i16_f32>;
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defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpknorm_u16_f32>;
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defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_I32_F32_F32>, AMDGPUpkrtz_f16_f32>;
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defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_I32_I32_I32>>;
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defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_I32_I32_I32>>;
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defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_I32_I32_I32>, AMDGPUpk_u16_u32>;
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defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_I32_I32_I32>, AMDGPUpk_i16_i32>;
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} // End SubtargetPredicate = isGCN
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@ -3264,6 +3264,18 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::amdgcn_cvt_pknorm_i16:
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case Intrinsic::amdgcn_cvt_pknorm_u16:
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case Intrinsic::amdgcn_cvt_pk_i16:
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case Intrinsic::amdgcn_cvt_pk_u16: {
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Value *Src0 = II->getArgOperand(0);
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Value *Src1 = II->getArgOperand(1);
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if (isa<UndefValue>(Src0) && isa<UndefValue>(Src1))
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return replaceInstUsesWith(*II, UndefValue::get(II->getType()));
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break;
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}
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case Intrinsic::amdgcn_ubfe:
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case Intrinsic::amdgcn_sbfe: {
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// Decompose simple cases into standard shifts.
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84
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
Normal file
84
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
Normal file
@ -0,0 +1,84 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}s_cvt_pk_i16_i32:
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; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}}
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; GCN-DAG: s_load_dword [[SY:s[0-9]+]], s[0:1], 0x{{c|30}}
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; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], [[SY]]
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; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, [[X]], [[VY]]
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; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, [[X]], [[VY]]
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define amdgpu_kernel void @s_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %y)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_cvt_pk_i16_samereg_i32:
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; GCN: s_load_dword [[X:s[0-9]+]]
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; GCN: v_cvt_pk_i16_i32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
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define amdgpu_kernel void @s_cvt_pk_i16_samereg_i32(i32 addrspace(1)* %out, i32 %x) #0 {
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 %x)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_i16_i32:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
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; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, [[A]], [[B]]
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; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, [[A]], [[B]]
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define amdgpu_kernel void @v_cvt_pk_i16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%b = load volatile i32, i32 addrspace(1)* %b.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 %b)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_i16_i32_reg_imm:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GCN: v_cvt_pk_i16_i32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1
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define amdgpu_kernel void @v_cvt_pk_i16_i32_reg_imm(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %a, i32 1)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_i16_i32_imm_reg:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; SI: v_cvt_pk_i16_i32_e32 v{{[0-9]+}}, 1, [[A]]
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; VI: v_cvt_pk_i16_i32 v{{[0-9]+}}, 1, [[A]]
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define amdgpu_kernel void @v_cvt_pk_i16_i32_imm_reg(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 1, i32 %a)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) #1
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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84
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
Normal file
84
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
Normal file
@ -0,0 +1,84 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pk_u16_u32:
|
||||
; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}}
|
||||
; GCN-DAG: s_load_dword [[SY:s[0-9]+]], s[0:1], 0x{{c|30}}
|
||||
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], [[SY]]
|
||||
; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
define amdgpu_kernel void @s_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pk_u16_samereg_i32:
|
||||
; GCN: s_load_dword [[X:s[0-9]+]]
|
||||
; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
|
||||
define amdgpu_kernel void @s_cvt_pk_u16_samereg_i32(i32 addrspace(1)* %out, i32 %x) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %x)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pk_u16_u32:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @v_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile i32, i32 addrspace(1)* %a.gep
|
||||
%b = load volatile i32, i32 addrspace(1)* %b.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 %b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_reg_imm:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1
|
||||
define amdgpu_kernel void @v_cvt_pk_u16_u32_reg_imm(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile i32, i32 addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 1)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_imm_reg:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, 1, [[A]]
|
||||
; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, 1, [[A]]
|
||||
define amdgpu_kernel void @v_cvt_pk_u16_u32_imm_reg(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile i32, i32 addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 1, i32 %a)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) #1
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
164
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
Normal file
164
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
Normal file
@ -0,0 +1,164 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pknorm_i16_f32:
|
||||
; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}}
|
||||
; GCN-DAG: s_load_dword [[SY:s[0-9]+]], s[0:1], 0x{{c|30}}
|
||||
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], [[SY]]
|
||||
; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
define amdgpu_kernel void @s_cvt_pknorm_i16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %y)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pknorm_i16_samereg_f32:
|
||||
; GCN: s_load_dword [[X:s[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
|
||||
define amdgpu_kernel void @s_cvt_pknorm_i16_samereg_f32(i32 addrspace(1)* %out, float %x) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float %x)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float %b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_reg_imm:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1.0
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_reg_imm(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float 1.0)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_imm_reg:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; SI: v_cvt_pknorm_i16_f32_e32 v{{[0-9]+}}, 1.0, [[A]]
|
||||
; VI: v_cvt_pknorm_i16_f32 v{{[0-9]+}}, 1.0, [[A]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_imm_reg(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float 1.0, float %a)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_lo:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], [[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_lo(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.a = fsub float -0.0, %a
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.a, float %b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_lo_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_lo_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.a = fsub float -0.0, %a
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_i16_f32_fneg_fabs_lo_fneg_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_i16_f32{{(_e64)*}} v{{[0-9]+}}, -|[[A]]|, -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_i16_f32_fneg_fabs_lo_fneg_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%fabs.a = call float @llvm.fabs.f32(float %a)
|
||||
%neg.fabs.a = fsub float -0.0, %fabs.a
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %neg.fabs.a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float, float) #1
|
||||
declare float @llvm.fabs.f32(float) #1
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
164
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
Normal file
164
test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
Normal file
@ -0,0 +1,164 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pknorm_u16_f32:
|
||||
; GCN-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x{{b|2c}}
|
||||
; GCN-DAG: s_load_dword [[SY:s[0-9]+]], s[0:1], 0x{{c|30}}
|
||||
; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], [[SY]]
|
||||
; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, [[X]], [[VY]]
|
||||
define amdgpu_kernel void @s_cvt_pknorm_u16_f32(i32 addrspace(1)* %out, float %x, float %y) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float %y)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_cvt_pknorm_u16_samereg_f32:
|
||||
; GCN: s_load_dword [[X:s[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
|
||||
define amdgpu_kernel void @s_cvt_pknorm_u16_samereg_f32(i32 addrspace(1)* %out, float %x) #0 {
|
||||
%result = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float %x)
|
||||
%r = bitcast <2 x i16> %result to i32
|
||||
store i32 %r, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, [[A]], [[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %a, float %b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_reg_imm:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1.0
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_reg_imm(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %a, float 1.0)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_imm_reg:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; SI: v_cvt_pknorm_u16_f32_e32 v{{[0-9]+}}, 1.0, [[A]]
|
||||
; VI: v_cvt_pknorm_u16_f32 v{{[0-9]+}}, 1.0, [[A]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_imm_reg(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float 1.0, float %a)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_fneg_lo:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], [[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_fneg_lo(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.a = fsub float -0.0, %a
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %neg.a, float %b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_fneg_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, [[A]], -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_fneg_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_fneg_lo_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, -[[A]], -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_fneg_lo_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%neg.a = fsub float -0.0, %a
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %neg.a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}v_cvt_pknorm_u16_f32_fneg_fabs_lo_fneg_hi:
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
|
||||
; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
|
||||
; GCN: v_cvt_pknorm_u16_f32{{(_e64)*}} v{{[0-9]+}}, -|[[A]]|, -[[B]]
|
||||
define amdgpu_kernel void @v_cvt_pknorm_u16_f32_fneg_fabs_lo_fneg_hi(i32 addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tid.ext = sext i32 %tid to i64
|
||||
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
||||
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
||||
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
|
||||
%a = load volatile float, float addrspace(1)* %a.gep
|
||||
%b = load volatile float, float addrspace(1)* %b.gep
|
||||
%fabs.a = call float @llvm.fabs.f32(float %a)
|
||||
%neg.fabs.a = fsub float -0.0, %fabs.a
|
||||
%neg.b = fsub float -0.0, %b
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %neg.fabs.a, float %neg.b)
|
||||
%r = bitcast <2 x i16> %cvt to i32
|
||||
store i32 %r, i32 addrspace(1)* %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float, float) #1
|
||||
declare float @llvm.fabs.f32(float) #1
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
||||
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readnone }
|
||||
@ -722,6 +722,114 @@ define <2 x half> @constant_rtz_pkrtz() {
|
||||
ret <2 x half> %cvt
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.cvt.pknorm.i16
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float, float) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: @undef_lhs_cvt_pknorm_i16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float %y)
|
||||
define <2 x i16> @undef_lhs_cvt_pknorm_i16(float %y) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float %y)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_rhs_cvt_pknorm_i16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float undef)
|
||||
define <2 x i16> @undef_rhs_cvt_pknorm_i16(float %x) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_cvt_pknorm_i16(
|
||||
; CHECK: ret <2 x i16> undef
|
||||
define <2 x i16> @undef_cvt_pknorm_i16() {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.cvt.pknorm.u16
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float, float) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: @undef_lhs_cvt_pknorm_u16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float %y)
|
||||
define <2 x i16> @undef_lhs_cvt_pknorm_u16(float %y) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float %y)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_rhs_cvt_pknorm_u16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float undef)
|
||||
define <2 x i16> @undef_rhs_cvt_pknorm_u16(float %x) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_cvt_pknorm_u16(
|
||||
; CHECK: ret <2 x i16> undef
|
||||
define <2 x i16> @undef_cvt_pknorm_u16() {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.cvt.pk.i16
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: @undef_lhs_cvt_pk_i16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 %y)
|
||||
define <2 x i16> @undef_lhs_cvt_pk_i16(i32 %y) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 %y)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_rhs_cvt_pk_i16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 undef)
|
||||
define <2 x i16> @undef_rhs_cvt_pk_i16(i32 %x) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_cvt_pk_i16(
|
||||
; CHECK: ret <2 x i16> undef
|
||||
define <2 x i16> @undef_cvt_pk_i16() {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.cvt.pk.u16
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: @undef_lhs_cvt_pk_u16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 %y)
|
||||
define <2 x i16> @undef_lhs_cvt_pk_u16(i32 %y) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 %y)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_rhs_cvt_pk_u16(
|
||||
; CHECK: %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 undef)
|
||||
define <2 x i16> @undef_rhs_cvt_pk_u16(i32 %x) {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @undef_cvt_pk_u16(
|
||||
; CHECK: ret <2 x i16> undef
|
||||
define <2 x i16> @undef_cvt_pk_u16() {
|
||||
%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 undef)
|
||||
ret <2 x i16> %cvt
|
||||
}
|
||||
|
||||
; --------------------------------------------------------------------
|
||||
; llvm.amdgcn.ubfe
|
||||
; --------------------------------------------------------------------
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user