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AMDGPU/GlobalISel: Don't use vector G_EXTRACT in arg lowering
Create a wider source vector, and unmerge with dead defs like the legalizer. The legalization handling for G_EXTRACT is incomplete, and it's preferrable to keep everything in 32-bit pieces. We should probably start moving these functions into utils, since we have a growing number of places that do almost the same thing.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
c7017bb445
commit
1356cf472c
@ -480,6 +480,43 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
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return true;
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}
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/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
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static MachineInstrBuilder mergeVectorRegsToResultRegs(
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MachineIRBuilder &B, ArrayRef<Register> DstRegs, ArrayRef<Register> SrcRegs) {
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MachineRegisterInfo &MRI = *B.getMRI();
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LLT LLTy = MRI.getType(DstRegs[0]);
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LLT PartLLT = MRI.getType(SrcRegs[0]);
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// Deal with v3s16 split into v2s16
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LLT LCMTy = getLCMType(LLTy, PartLLT);
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if (LCMTy == LLTy) {
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// Common case where no padding is needed.
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assert(DstRegs.size() == 1);
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return B.buildConcatVectors(DstRegs[0], SrcRegs);
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}
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const int NumWide = LCMTy.getSizeInBits() / PartLLT.getSizeInBits();
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Register Undef = B.buildUndef(PartLLT).getReg(0);
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// Build vector of undefs.
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SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);
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// Replace the first sources with the real registers.
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std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());
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auto Widened = B.buildConcatVectors(LCMTy, WidenedSrcs);
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int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
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SmallVector<Register, 8> PadDstRegs(NumDst);
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std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
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// Create the excess dead defs for the unmerge.
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for (int I = DstRegs.size(); I != NumDst; ++I)
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PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
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return B.buildUnmerge(PadDstRegs, Widened);
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}
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// TODO: Move this to generic code
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static void packSplitRegsToOrigType(MachineIRBuilder &B,
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ArrayRef<Register> OrigRegs,
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@ -492,22 +529,9 @@ static void packSplitRegsToOrigType(MachineIRBuilder &B,
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}
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if (LLTy.isVector() && PartLLT.isVector()) {
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assert(OrigRegs.size() == 1);
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assert(LLTy.getElementType() == PartLLT.getElementType());
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int DstElts = LLTy.getNumElements();
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int PartElts = PartLLT.getNumElements();
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if (DstElts % PartElts == 0)
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B.buildConcatVectors(OrigRegs[0], Regs);
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else {
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// Deal with v3s16 split into v2s16
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assert(PartElts == 2 && DstElts % 2 != 0);
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int RoundedElts = PartElts * ((DstElts + PartElts - 1) / PartElts);
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LLT RoundedDestTy = LLT::vector(RoundedElts, PartLLT.getElementType());
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auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs);
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B.buildExtract(OrigRegs[0], RoundedConcat, 0);
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}
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mergeVectorRegsToResultRegs(B, OrigRegs, Regs);
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return;
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}
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@ -814,10 +814,11 @@ define void @void_func_v3i16(<3 x i16> %arg0) #0 {
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
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; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
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; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[EXTRACT]](<3 x s16>), [[DEF]](p1) :: (store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)
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; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
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; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]]
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store <3 x i16> %arg0, <3 x i16> addrspace(1)* undef
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@ -848,10 +849,11 @@ define void @void_func_v5i16(<5 x i16> %arg0) #0 {
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>)
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; CHECK: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
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; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[EXTRACT]](<5 x s16>), [[DEF]](p1) :: (store 10 into `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
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; CHECK: [[UV:%[0-9]+]]:_(<5 x s16>), [[UV1:%[0-9]+]]:_(<5 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<10 x s16>)
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; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[UV]](<5 x s16>), [[DEF1]](p1) :: (store 10 into `<5 x i16> addrspace(1)* undef`, align 16, addrspace 1)
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; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
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; CHECK: S_SETPC_B64_return [[COPY4]]
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store <5 x i16> %arg0, <5 x i16> addrspace(1)* undef
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@ -898,6 +900,58 @@ define void @void_func_v16i16(<16 x i16> %arg0) #0 {
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ret void
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}
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; <2 x i16> pieces that start spilling to the stack.
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; FIXME: load of 2 would be sufficient for last piece
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define void @void_func_v65i16(<65 x i16> %arg0) #0 {
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; CHECK-LABEL: name: void_func_v65i16
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr4
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; CHECK: [[COPY5:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr5
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; CHECK: [[COPY6:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr6
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; CHECK: [[COPY7:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr7
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; CHECK: [[COPY8:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr8
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; CHECK: [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr9
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; CHECK: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr10
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; CHECK: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr11
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; CHECK: [[COPY12:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr12
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; CHECK: [[COPY13:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr13
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; CHECK: [[COPY14:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr14
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; CHECK: [[COPY15:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr15
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; CHECK: [[COPY16:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr16
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; CHECK: [[COPY17:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr17
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; CHECK: [[COPY18:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr18
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; CHECK: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr19
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; CHECK: [[COPY20:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr20
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; CHECK: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr21
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; CHECK: [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr22
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; CHECK: [[COPY23:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr23
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; CHECK: [[COPY24:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr24
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; CHECK: [[COPY25:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr25
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; CHECK: [[COPY26:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr26
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; CHECK: [[COPY27:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr27
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; CHECK: [[COPY28:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr28
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; CHECK: [[COPY29:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr29
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; CHECK: [[COPY30:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr30
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; CHECK: [[COPY31:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr31
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5)
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; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>), [[COPY8]](<2 x s16>), [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[COPY12]](<2 x s16>), [[COPY13]](<2 x s16>), [[COPY14]](<2 x s16>), [[COPY15]](<2 x s16>), [[COPY16]](<2 x s16>), [[COPY17]](<2 x s16>), [[COPY18]](<2 x s16>), [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[COPY23]](<2 x s16>), [[COPY24]](<2 x s16>), [[COPY25]](<2 x s16>), [[COPY26]](<2 x s16>), [[COPY27]](<2 x s16>), [[COPY28]](<2 x s16>), [[COPY29]](<2 x s16>), [[COPY30]](<2 x s16>), [[COPY31]](<2 x s16>), [[LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
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; CHECK: [[UV:%[0-9]+]]:_(<65 x s16>), [[UV1:%[0-9]+]]:_(<65 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)
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; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[UV]](<65 x s16>), [[DEF1]](p1) :: (store 130 into `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)
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; CHECK: [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
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; CHECK: S_SETPC_B64_return [[COPY33]]
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store <65 x i16> %arg0, <65 x i16> addrspace(1)* undef
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ret void
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}
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define void @void_func_v2f32(<2 x float> %arg0) #0 {
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; CHECK-LABEL: name: void_func_v2f32
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; CHECK: bb.1 (%ir-block.0):
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@ -1191,10 +1245,11 @@ define void @void_func_v3f16(<3 x half> %arg0) #0 {
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
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; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
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; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[EXTRACT]](<3 x s16>), [[DEF]](p1) :: (store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
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; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[DEF]](<2 x s16>)
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; CHECK: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
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; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: G_STORE [[UV]](<3 x s16>), [[DEF1]](p1) :: (store 6 into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]]
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store <3 x half> %arg0, <3 x half> addrspace(1)* undef
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@ -105,15 +105,16 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
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; UNPACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
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; UNPACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
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; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
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; UNPACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
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; UNPACKED: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
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; UNPACKED: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
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; UNPACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
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; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
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; UNPACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
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; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0
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; UNPACKED: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
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; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
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; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
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; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
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; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
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; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
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; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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@ -137,9 +138,10 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
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; PACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
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; PACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3
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; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>)
|
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; PACKED: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
|
||||
; PACKED: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[EXTRACT]](<3 x s16>), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
|
||||
; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
|
||||
; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>)
|
||||
; PACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
|
||||
; PACKED: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.image.store.2d), [[UV]](<3 x s16>), 7, [[COPY8]](s32), [[COPY9]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8)
|
||||
; PACKED: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
|
||||
Loading…
Reference in New Issue
Block a user