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[Hexagon] Move isTypeForHVX from Hexagon TTI to HexagonSubtarget, NFC
It's useful outside of Hexagon TTI, and with how TTI is implemented, it is not accessible outside of TTI.
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@ -125,6 +125,59 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
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return *this;
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}
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bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
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if (!useHVXOps())
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return false;
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if (Ty.isVector())
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Ty = Ty.getVectorElementType();
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if (IncludeBool && Ty == MVT::i1)
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return true;
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ArrayRef<MVT> ElemTypes = getHVXElementTypes();
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return llvm::find(ElemTypes, Ty) != ElemTypes.end();
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}
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bool HexagonSubtarget::isHVXVectorType(MVT VecTy, bool IncludeBool) const {
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if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
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return false;
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MVT ElemTy = VecTy.getVectorElementType();
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if (!IncludeBool && ElemTy == MVT::i1)
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return false;
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unsigned HwLen = getVectorLength();
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unsigned NumElems = VecTy.getVectorNumElements();
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ArrayRef<MVT> ElemTypes = getHVXElementTypes();
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if (IncludeBool && ElemTy == MVT::i1) {
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// Boolean HVX vector types are formed from regular HVX vector types
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// by replacing the element type with i1.
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for (MVT T : ElemTypes)
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if (NumElems * T.getSizeInBits() == 8 * HwLen)
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return true;
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return false;
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}
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unsigned VecWidth = VecTy.getSizeInBits();
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if (VecWidth != 8 * HwLen && VecWidth != 16 * HwLen)
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return false;
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return llvm::find(ElemTypes, ElemTy) != ElemTypes.end();
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}
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bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
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if (!VecTy->isVectorTy() || isa<ScalableVectorType>(VecTy))
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return false;
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// Avoid types like <2 x i32*>.
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if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy())
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return false;
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EVT Ty = EVT::getEVT(VecTy, /*HandleUnknown*/false);
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if (!Ty.isSimple() || Ty.getSizeInBits() <= 64)
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return false;
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if (isHVXVectorType(Ty.getSimpleVT(), IncludeBool))
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return true;
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auto Action =
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getTargetLowering()->getPreferredVectorAction(Ty.getSimpleVT());
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return Action == TargetLoweringBase::TypeWidenVector;
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}
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void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {
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for (SUnit &SU : DAG->SUnits) {
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if (!SU.isInstr())
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@ -275,42 +275,9 @@ public:
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return makeArrayRef(Types);
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}
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bool isHVXElementType(MVT Ty, bool IncludeBool = false) const {
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if (!useHVXOps())
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return false;
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if (Ty.isVector())
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Ty = Ty.getVectorElementType();
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if (IncludeBool && Ty == MVT::i1)
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return true;
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ArrayRef<MVT> ElemTypes = getHVXElementTypes();
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return llvm::find(ElemTypes, Ty) != ElemTypes.end();
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}
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bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const {
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if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
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return false;
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MVT ElemTy = VecTy.getVectorElementType();
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if (!IncludeBool && ElemTy == MVT::i1)
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return false;
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unsigned HwLen = getVectorLength();
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unsigned NumElems = VecTy.getVectorNumElements();
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ArrayRef<MVT> ElemTypes = getHVXElementTypes();
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if (IncludeBool && ElemTy == MVT::i1) {
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// Boolean HVX vector types are formed from regular HVX vector types
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// by replacing the element type with i1.
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for (MVT T : ElemTypes)
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if (NumElems * T.getSizeInBits() == 8*HwLen)
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return true;
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return false;
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}
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unsigned VecWidth = VecTy.getSizeInBits();
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if (VecWidth != 8*HwLen && VecWidth != 16*HwLen)
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return false;
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return llvm::find(ElemTypes, ElemTy) != ElemTypes.end();
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}
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bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
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bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const;
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bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
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unsigned getTypeAlignment(MVT Ty) const {
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if (isHVXVectorType(Ty, true))
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@ -47,21 +47,6 @@ bool HexagonTTIImpl::useHVX() const {
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return ST.useHVXOps() && HexagonAutoHVX;
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}
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bool HexagonTTIImpl::isTypeForHVX(Type *VecTy) const {
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if (!VecTy->isVectorTy() || isa<ScalableVectorType>(VecTy))
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return false;
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// Avoid types like <2 x i32*>.
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if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy())
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return false;
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EVT VecVT = EVT::getEVT(VecTy);
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if (!VecVT.isSimple() || VecVT.getSizeInBits() <= 64)
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return false;
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if (ST.isHVXVectorType(VecVT.getSimpleVT()))
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return true;
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auto Action = TLI.getPreferredVectorAction(VecVT.getSimpleVT());
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return Action == TargetLoweringBase::TypeWidenVector;
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}
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unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
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if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
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return VTy->getNumElements();
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@ -171,7 +156,7 @@ unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
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if (Src->isVectorTy()) {
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VectorType *VecTy = cast<VectorType>(Src);
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unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
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if (useHVX() && isTypeForHVX(VecTy)) {
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if (useHVX() && ST.isTypeForHVX(VecTy)) {
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unsigned RegWidth = getRegisterBitWidth(true);
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assert(RegWidth && "Non-zero vector register width expected");
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// Cost of HVX loads.
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@ -314,11 +299,11 @@ unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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}
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bool HexagonTTIImpl::isLegalMaskedStore(Type *DataType, Align /*Alignment*/) {
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return HexagonMaskedVMem && isTypeForHVX(DataType);
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return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
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}
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bool HexagonTTIImpl::isLegalMaskedLoad(Type *DataType, Align /*Alignment*/) {
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return HexagonMaskedVMem && isTypeForHVX(DataType);
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return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
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}
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/// --- Vector TTI end ---
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@ -43,7 +43,6 @@ class HexagonTTIImpl : public BasicTTIImplBase<HexagonTTIImpl> {
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const HexagonTargetLowering *getTLI() const { return &TLI; }
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bool useHVX() const;
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bool isTypeForHVX(Type *VecTy) const;
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// Returns the number of vector elements of Ty, if Ty is a vector type,
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// or 1 if Ty is a scalar type. It is incorrect to call this function
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