[NFC] fix trivial typos in comments

"the the" -> "the"

llvm-svn: 323302

lib/Target/AMDGPU/SIInstrInfo.h

@@ -44,7 +44,7 @@ private:
   const SIRegisterInfo RI;
   const SISubtarget &ST;
 
-  // The the inverse predicate should have the negative value.
+  // The inverse predicate should have the negative value.
   enum BranchPredicate {
     INVALID_BR = 0,
     SCC_TRUE = 1,

test/CodeGen/AArch64/arm64-stp-aa.ll

@@ -112,7 +112,7 @@ define double @stp_double_aa_after(double %d0, double %a, double %b, double* noc
 
 ; Check that the stores %c and %d are paired after the fadd instruction,
 ; and then the stores %a and %d are paired after proving that they do not
-; depend on the the (%c, %d) pair.
+; depend on the (%c, %d) pair.
 ;
 ; CHECK-LABEL: st1:
 ; CHECK: stp q0, q1, [x{{[0-9]+}}]

test/CodeGen/AMDGPU/sgpr-copy.ll

@@ -379,7 +379,7 @@ bb71:                                             ; preds = %bb80, %bb38
   ret void
 }
 
-; Check the the resource descriptor is stored in an sgpr.
+; Check the resource descriptor is stored in an sgpr.
 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
 define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
@@ -394,7 +394,7 @@ bb:
   ret void
 }
 
-; Check the the sampler is stored in an sgpr.
+; Check the sampler is stored in an sgpr.
 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
 define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {

test/CodeGen/Hexagon/swp-epilog-reuse-1.ll

@@ -4,7 +4,7 @@
 ; Test that the pipeliner reuses an existing Phi when generating the epilog
 ; block. In this case, the original loops has a Phi whose operand is another
 ; Phi. When the loop is pipelined, the Phi that generates the operand value
-; is used in two stages. This means the the Phi for the second stage can
+; is used in two stages. This means the Phi for the second stage can
 ; be reused. The bug causes an assert due to an invalid virtual register error
 ; in the live variable analysis.
 

test/CodeGen/Mips/cconv/callee-saved-float.ll

@@ -20,7 +20,7 @@
 
 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
 
-; Test the the callee-saved registers are callee-saved as specified by section
+; Test the callee-saved registers are callee-saved as specified by section
 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
 
 define void @fpu_clobber() nounwind {

test/Transforms/GVN/PRE/load-pre-licm.ll

@@ -88,7 +88,7 @@ merge:
 ; TODO: at the moment, our anticipation check does not handle anything
 ; other than straight-line unconditional fallthrough.  This particular
 ; case could be solved through either a backwards anticipation walk or
-; use of the the "safe to speculate" status (if we annotate the param)
+; use of the "safe to speculate" status (if we annotate the param)
 define i32 @test3(i1 %cnd, i32* %p) {
 entry: 
 ; CHECK-LABEL: @test3

utils/TableGen/GlobalISelEmitter.cpp

@@ -2651,7 +2651,7 @@ private:
 
   /// Takes a sequence of \p Rules and group them based on the predicates
   /// they share. \p StorageGroupMatcher is used as a memory container
-  /// for the the group that are created as part of this process.
+  /// for the group that are created as part of this process.
   /// The optimization process does not change the relative order of
   /// the rules. In particular, we don't try to share predicates if
   /// that means reordering the rules (e.g., we won't group R1 and R3