From 141d1c9004324c0d80bb7ffa9f2ce1275a8df515 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 4 Jul 2018 13:58:13 +0000 Subject: [PATCH] [X86][SSE] Add SSE2 target to some shift tests Show the difference in behaviour cf SSE41 (no PMULLD, PBLENDW etc.) Raised by D48936 llvm-svn: 336271 --- test/CodeGen/X86/combine-shl.ll | 555 ++++++++++++++++++++++-------- test/CodeGen/X86/vec_shift6.ll | 257 ++++++++------ test/CodeGen/X86/widen_arith-4.ll | 101 ++++-- 3 files changed, 638 insertions(+), 275 deletions(-) diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll index 4184de12a3c..70386bb9aef 100644 --- a/test/CodeGen/X86/combine-shl.ll +++ b/test/CodeGen/X86/combine-shl.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX-FAST @@ -70,11 +71,24 @@ define <4 x i32> @combine_vec_shl_known_zero0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_known_zero1: -; SSE: # %bb.0: -; SSE-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_known_zero1: +; SSE2: # %bb.0: +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65536,32768,16384,8192] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_known_zero1: +; SSE41: # %bb.0: +; SSE41-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_known_zero1: ; AVX: # %bb.0: @@ -88,15 +102,31 @@ define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) { ; fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) { -; SSE-LABEL: combine_vec_shl_trunc_and: -; SSE: # %bb.0: -; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] -; SSE-NEXT: andps {{.*}}(%rip), %xmm1 -; SSE-NEXT: pslld $23, %xmm1 -; SSE-NEXT: paddd {{.*}}(%rip), %xmm1 -; SSE-NEXT: cvttps2dq %xmm1, %xmm1 -; SSE-NEXT: pmulld %xmm1, %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_trunc_and: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] +; SSE2-NEXT: andps {{.*}}(%rip), %xmm1 +; SSE2-NEXT: pslld $23, %xmm1 +; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1 +; SSE2-NEXT: cvttps2dq %xmm1, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_trunc_and: +; SSE41: # %bb.0: +; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] +; SSE41-NEXT: andps {{.*}}(%rip), %xmm1 +; SSE41-NEXT: pslld $23, %xmm1 +; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1 +; SSE41-NEXT: cvttps2dq %xmm1, %xmm1 +; SSE41-NEXT: pmulld %xmm1, %xmm0 +; SSE41-NEXT: retq ; ; AVX-SLOW-LABEL: combine_vec_shl_trunc_and: ; AVX-SLOW: # %bb.0: @@ -138,10 +168,22 @@ define <4 x i32> @combine_vec_shl_shl0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_shl1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_shl1: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_shl1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,64,256,1024] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_shl1: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_shl1: ; AVX: # %bb.0: @@ -185,14 +227,23 @@ define <4 x i32> @combine_vec_shl_shl_zero1(<4 x i32> %x) { ; fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) { -; SSE-LABEL: combine_vec_shl_ext_shl0: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero -; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] -; SSE-NEXT: pslld $20, %xmm1 -; SSE-NEXT: pslld $20, %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_ext_shl0: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] +; SSE2-NEXT: pslld $20, %xmm0 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; SSE2-NEXT: pslld $20, %xmm1 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_ext_shl0: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; SSE41-NEXT: pslld $20, %xmm1 +; SSE41-NEXT: pslld $20, %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ext_shl0: ; AVX: # %bb.0: @@ -206,15 +257,40 @@ define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) { } define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) { -; SSE-LABEL: combine_vec_shl_ext_shl1: -; SSE: # %bb.0: -; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; SSE-NEXT: pmovsxwd %xmm1, %xmm1 -; SSE-NEXT: pmovsxwd %xmm0, %xmm0 -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_ext_shl1: +; SSE2: # %bb.0: +; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; SSE2-NEXT: psrad $16, %xmm1 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] +; SSE2-NEXT: psrad $16, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,1073741824,1073741824] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm3, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [536870912,536870912,268435456,268435456] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm3, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_ext_shl1: +; SSE41: # %bb.0: +; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0 +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] +; SSE41-NEXT: pmovsxwd %xmm1, %xmm1 +; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ext_shl1: ; AVX: # %bb.0: @@ -230,14 +306,24 @@ define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) { ; fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C)) define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) { -; SSE-LABEL: combine_vec_shl_zext_lshr0: -; SSE: # %bb.0: -; SSE-NEXT: pand {{.*}}(%rip), %xmm0 -; SSE-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero -; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] -; SSE-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero -; SSE-NEXT: movdqa %xmm2, %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_zext_lshr0: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_zext_lshr0: +; SSE41: # %bb.0: +; SSE41-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_zext_lshr0: ; AVX: # %bb.0: @@ -251,26 +337,74 @@ define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) { } define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) { -; SSE-LABEL: combine_vec_shl_zext_lshr1: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrlw $8, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,6],xmm1[7] -; SSE-NEXT: movdqa %xmm1, %xmm0 -; SSE-NEXT: psrlw $4, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6],xmm1[7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrlw $2, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3,4],xmm1[5,6],xmm0[7] -; SSE-NEXT: movdqa %xmm1, %xmm0 -; SSE-NEXT: psrlw $1, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; SSE-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero -; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_zext_lshr1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,65535,0] +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: pand %xmm1, %xmm2 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: pandn %xmm0, %xmm1 +; SSE2-NEXT: por %xmm2, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,0,0,0,0,65535] +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: psrlw $4, %xmm1 +; SSE2-NEXT: pandn %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,0,0,65535,65535,0] +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psrlw $2, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,16] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm3, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32,64,128,256] +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm3, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_zext_lshr1: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrlw $8, %xmm1 +; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,6],xmm1[7] +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: psrlw $4, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6],xmm1[7] +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrlw $2, %xmm1 +; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3,4],xmm1[5,6],xmm0[7] +; SSE41-NEXT: movdqa %xmm1, %xmm0 +; SSE41-NEXT: psrlw $1, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_zext_lshr1: ; AVX: # %bb.0: @@ -305,20 +439,44 @@ define <4 x i32> @combine_vec_shl_ge_ashr_extact0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_ge_ashr_extact1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_ge_ashr_extact1: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $8, %xmm1 -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: psrad $4, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $5, %xmm1 -; SSE-NEXT: psrad $3, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_ge_ashr_extact1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrad $8, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psrad $5, %xmm2 +; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1] +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrad $4, %xmm1 +; SSE2-NEXT: psrad $3, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3] +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32,64,128,256] +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_ge_ashr_extact1: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrad $8, %xmm1 +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psrad $4, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrad $5, %xmm1 +; SSE41-NEXT: psrad $3, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ge_ashr_extact1: ; AVX: # %bb.0: @@ -347,20 +505,44 @@ define <4 x i32> @combine_vec_shl_lt_ashr_extact0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_lt_ashr_extact1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_lt_ashr_extact1: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $8, %xmm1 -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: psrad $6, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $7, %xmm1 -; SSE-NEXT: psrad $5, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_lt_ashr_extact1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrad $8, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psrad $7, %xmm2 +; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1] +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrad $6, %xmm1 +; SSE2-NEXT: psrad $5, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3] +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,16,32,256] +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_lt_ashr_extact1: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrad $8, %xmm1 +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psrad $6, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrad $7, %xmm1 +; SSE41-NEXT: psrad $5, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_lt_ashr_extact1: ; AVX: # %bb.0: @@ -392,20 +574,44 @@ define <4 x i32> @combine_vec_shl_gt_lshr0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_gt_lshr1: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $8, %xmm1 -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: psrld $4, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $5, %xmm1 -; SSE-NEXT: psrld $3, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_gt_lshr1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrld $8, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psrld $5, %xmm2 +; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1] +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrld $4, %xmm1 +; SSE2-NEXT: psrld $3, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3] +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32,64,128,256] +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_gt_lshr1: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrld $8, %xmm1 +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psrld $4, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrld $5, %xmm1 +; SSE41-NEXT: psrld $3, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_gt_lshr1: ; AVX: # %bb.0: @@ -437,20 +643,44 @@ define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_le_lshr1: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $8, %xmm1 -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: psrld $6, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrld $7, %xmm1 -; SSE-NEXT: psrld $5, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_le_lshr1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrld $8, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: psrld $7, %xmm2 +; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1] +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrld $6, %xmm1 +; SSE2-NEXT: psrld $5, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3] +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,16,32,256] +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_le_lshr1: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrld $8, %xmm1 +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: psrld $6, %xmm2 +; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psrld $7, %xmm1 +; SSE41-NEXT: psrld $5, %xmm0 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_le_lshr1: ; AVX: # %bb.0: @@ -514,11 +744,24 @@ define <4 x i32> @combine_vec_shl_add0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_add1: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: paddd {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_add1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,16] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_add1: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: paddd {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_add1: ; AVX: # %bb.0: @@ -550,11 +793,24 @@ define <4 x i32> @combine_vec_shl_or0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_or1: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: por {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_or1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,16] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: por {{.*}}(%rip), %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_or1: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: por {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_or1: ; AVX: # %bb.0: @@ -568,10 +824,21 @@ define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) { ; fold (shl (mul x, c1), c2) -> (mul x, c1 << c2) define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_mul0: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_mul0: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [20,20,20,20] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_mul0: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_mul0: ; AVX: # %bb.0: @@ -584,10 +851,22 @@ define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) { } define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) { -; SSE-LABEL: combine_vec_shl_mul1: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: combine_vec_shl_mul1: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [10,24,56,128] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq +; +; SSE41-LABEL: combine_vec_shl_mul1: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_mul1: ; AVX: # %bb.0: diff --git a/test/CodeGen/X86/vec_shift6.ll b/test/CodeGen/X86/vec_shift6.ll index db8ef0b213c..7f2e1e5c2f7 100644 --- a/test/CodeGen/X86/vec_shift6.ll +++ b/test/CodeGen/X86/vec_shift6.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse4.1 | FileCheck %s --check-prefix=SSE -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s --check-prefix=AVX2 -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s --check-prefix=AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse2 | FileCheck %s --check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s --check-prefixes=AVX,AVX512 ; Verify that we don't scalarize a packed vector shift left of 16-bit ; signed integers if the amount is a constant build_vector. @@ -13,15 +14,10 @@ define <8 x i16> @test1(<8 x i16> %a) { ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; -; AVX2-LABEL: test1: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: retq -; -; AVX512-LABEL: test1: -; AVX512: # %bb.0: -; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; AVX512-NEXT: retq +; AVX-LABEL: test1: +; AVX: # %bb.0: +; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %shl = shl <8 x i16> %a, ret <8 x i16> %shl } @@ -32,15 +28,10 @@ define <8 x i16> @test2(<8 x i16> %a) { ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; -; AVX2-LABEL: test2: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: retq -; -; AVX512-LABEL: test2: -; AVX512: # %bb.0: -; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; AVX512-NEXT: retq +; AVX-LABEL: test2: +; AVX: # %bb.0: +; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %shl = shl <8 x i16> %a, ret <8 x i16> %shl } @@ -50,39 +41,51 @@ define <8 x i16> @test2(<8 x i16> %a) { ; counts is a constant build_vector. define <4 x i32> @test3(<4 x i32> %a) { -; SSE-LABEL: test3: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: test3: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm0, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq ; -; AVX2-LABEL: test3: -; AVX2: # %bb.0: -; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: retq +; SSE41-LABEL: test3: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; -; AVX512-LABEL: test3: -; AVX512: # %bb.0: -; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 -; AVX512-NEXT: retq +; AVX-LABEL: test3: +; AVX: # %bb.0: +; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %shl = shl <4 x i32> %a, ret <4 x i32> %shl } define <4 x i32> @test4(<4 x i32> %a) { -; SSE-LABEL: test4: -; SSE: # %bb.0: -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 -; SSE-NEXT: retq +; SSE2-LABEL: test4: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,1,2,2] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: retq ; -; AVX2-LABEL: test4: -; AVX2: # %bb.0: -; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: retq +; SSE41-LABEL: test4: +; SSE41: # %bb.0: +; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE41-NEXT: retq ; -; AVX512-LABEL: test4: -; AVX512: # %bb.0: -; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 -; AVX512-NEXT: retq +; AVX-LABEL: test4: +; AVX: # %bb.0: +; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %shl = shl <4 x i32> %a, ret <4 x i32> %shl } @@ -99,15 +102,10 @@ define <16 x i16> @test5(<16 x i16> %a) { ; SSE-NEXT: pmullw %xmm2, %xmm1 ; SSE-NEXT: retq ; -; AVX2-LABEL: test5: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: retq -; -; AVX512-LABEL: test5: -; AVX512: # %bb.0: -; AVX512-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 -; AVX512-NEXT: retq +; AVX-LABEL: test5: +; AVX: # %bb.0: +; AVX-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 +; AVX-NEXT: retq %shl = shl <16 x i16> %a, ret <16 x i16> %shl } @@ -117,22 +115,36 @@ define <16 x i16> @test5(<16 x i16> %a) { ; a single vpsllvd instead. define <8 x i32> @test6(<8 x i32> %a) { -; SSE-LABEL: test6: -; SSE: # %bb.0: -; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,2,4,8] -; SSE-NEXT: pmulld %xmm2, %xmm0 -; SSE-NEXT: pmulld %xmm2, %xmm1 -; SSE-NEXT: retq +; SSE2-LABEL: test6: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2,2,4,8] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm2, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] +; SSE2-NEXT: pmuludq %xmm1, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: retq ; -; AVX2-LABEL: test6: -; AVX2: # %bb.0: -; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: retq +; SSE41-LABEL: test6: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2,2,4,8] +; SSE41-NEXT: pmulld %xmm2, %xmm0 +; SSE41-NEXT: pmulld %xmm2, %xmm1 +; SSE41-NEXT: retq ; -; AVX512-LABEL: test6: -; AVX512: # %bb.0: -; AVX512-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 -; AVX512-NEXT: retq +; AVX-LABEL: test6: +; AVX: # %bb.0: +; AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 +; AVX-NEXT: retq %shl = shl <8 x i32> %a, ret <8 x i32> %shl } @@ -151,21 +163,13 @@ define <32 x i16> @test7(<32 x i16> %a) { ; SSE-NEXT: pmullw %xmm4, %xmm3 ; SSE-NEXT: retq ; -; AVX2-LABEL: test7: -; AVX2: # %bb.0: -; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,4,8,128,1,512,2048,2,2,4,8,128,1,512,2048] -; AVX2-NEXT: # ymm2 = mem[0,1,0,1] -; AVX2-NEXT: vpmullw %ymm2, %ymm0, %ymm0 -; AVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1 -; AVX2-NEXT: retq -; -; AVX512-LABEL: test7: -; AVX512: # %bb.0: -; AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,4,8,128,1,512,2048,2,2,4,8,128,1,512,2048] -; AVX512-NEXT: # ymm2 = mem[0,1,0,1] -; AVX512-NEXT: vpmullw %ymm2, %ymm0, %ymm0 -; AVX512-NEXT: vpmullw %ymm2, %ymm1, %ymm1 -; AVX512-NEXT: retq +; AVX-LABEL: test7: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [2,2,4,8,128,1,512,2048,2,2,4,8,128,1,512,2048] +; AVX-NEXT: # ymm2 = mem[0,1,0,1] +; AVX-NEXT: vpmullw %ymm2, %ymm0, %ymm0 +; AVX-NEXT: vpmullw %ymm2, %ymm1, %ymm1 +; AVX-NEXT: retq %shl = shl <32 x i16> %a, ret <32 x i16> %shl } @@ -174,14 +178,45 @@ define <32 x i16> @test7(<32 x i16> %a) { ; we only produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq. define <16 x i32> @test8(<16 x i32> %a) { -; SSE-LABEL: test8: -; SSE: # %bb.0: -; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2,2,4,8] -; SSE-NEXT: pmulld %xmm4, %xmm0 -; SSE-NEXT: pmulld %xmm4, %xmm1 -; SSE-NEXT: pmulld %xmm4, %xmm2 -; SSE-NEXT: pmulld %xmm4, %xmm3 -; SSE-NEXT: retq +; SSE2-LABEL: test8: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2,2,4,8] +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm6, %xmm5 +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: pmuludq %xmm6, %xmm5 +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: pmuludq %xmm6, %xmm5 +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1] +; SSE2-NEXT: pmuludq %xmm3, %xmm4 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; SSE2-NEXT: pmuludq %xmm6, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] +; SSE2-NEXT: movdqa %xmm4, %xmm3 +; SSE2-NEXT: retq +; +; SSE41-LABEL: test8: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [2,2,4,8] +; SSE41-NEXT: pmulld %xmm4, %xmm0 +; SSE41-NEXT: pmulld %xmm4, %xmm1 +; SSE41-NEXT: pmulld %xmm4, %xmm2 +; SSE41-NEXT: pmulld %xmm4, %xmm3 +; SSE41-NEXT: retq ; ; AVX2-LABEL: test8: ; AVX2: # %bb.0: @@ -202,19 +237,33 @@ define <16 x i32> @test8(<16 x i32> %a) { ; The shift from 'test9' gets shifted separately and blended if we don't have AVX2/AVX512f support. define <8 x i64> @test9(<8 x i64> %a) { -; SSE-LABEL: test9: -; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm1, %xmm4 -; SSE-NEXT: psllq $3, %xmm4 -; SSE-NEXT: psllq $2, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7] -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psllq $3, %xmm4 -; SSE-NEXT: psllq $2, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7] -; SSE-NEXT: paddq %xmm0, %xmm0 -; SSE-NEXT: paddq %xmm2, %xmm2 -; SSE-NEXT: retq +; SSE2-LABEL: test9: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: psllq $2, %xmm4 +; SSE2-NEXT: psllq $3, %xmm1 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm4[0],xmm1[1] +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: psllq $2, %xmm4 +; SSE2-NEXT: psllq $3, %xmm3 +; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm4[0],xmm3[1] +; SSE2-NEXT: paddq %xmm0, %xmm0 +; SSE2-NEXT: paddq %xmm2, %xmm2 +; SSE2-NEXT: retq +; +; SSE41-LABEL: test9: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm1, %xmm4 +; SSE41-NEXT: psllq $3, %xmm4 +; SSE41-NEXT: psllq $2, %xmm1 +; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7] +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psllq $3, %xmm4 +; SSE41-NEXT: psllq $2, %xmm3 +; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7] +; SSE41-NEXT: paddq %xmm0, %xmm0 +; SSE41-NEXT: paddq %xmm2, %xmm2 +; SSE41-NEXT: retq ; ; AVX2-LABEL: test9: ; AVX2: # %bb.0: diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll index 31e18ac54ce..a38b12a759d 100644 --- a/test/CodeGen/X86/widen_arith-4.ll +++ b/test/CodeGen/X86/widen_arith-4.ll @@ -1,41 +1,76 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE41 ; Widen a v5i16 to v8i16 to do a vector sub and multiple define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind { -; CHECK-LABEL: update: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movl %edx, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movq {{.*}}(%rip), %rax -; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movw $0, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u> -; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <2,4,2,2,2,u,u,u> -; CHECK-NEXT: jmp .LBB0_1 -; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_2: # %forbody -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rax -; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx -; CHECK-NEXT: shlq $4, %rax -; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx -; CHECK-NEXT: movdqa (%rdx,%rax), %xmm2 -; CHECK-NEXT: psubw %xmm0, %xmm2 -; CHECK-NEXT: pmullw %xmm1, %xmm2 -; CHECK-NEXT: pextrw $4, %xmm2, 8(%rcx,%rax) -; CHECK-NEXT: movq %xmm2, (%rcx,%rax) -; CHECK-NEXT: incl -{{[0-9]+}}(%rsp) -; CHECK-NEXT: .LBB0_1: # %forcond -; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax -; CHECK-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax -; CHECK-NEXT: jl .LBB0_2 -; CHECK-NEXT: # %bb.3: # %afterfor -; CHECK-NEXT: retq +; SSE2-LABEL: update: +; SSE2: # %bb.0: # %entry +; SSE2-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movl %edx, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movq {{.*}}(%rip), %rax +; SSE2-NEXT: movq %rax, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movw $0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movl $0, -{{[0-9]+}}(%rsp) +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u> +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = <2,4,2,2,2,u,u,u> +; SSE2-NEXT: jmp .LBB0_1 +; SSE2-NEXT: .p2align 4, 0x90 +; SSE2-NEXT: .LBB0_2: # %forbody +; SSE2-NEXT: # in Loop: Header=BB0_1 Depth=1 +; SSE2-NEXT: movslq -{{[0-9]+}}(%rsp), %rax +; SSE2-NEXT: movq -{{[0-9]+}}(%rsp), %rcx +; SSE2-NEXT: shlq $4, %rax +; SSE2-NEXT: movq -{{[0-9]+}}(%rsp), %rdx +; SSE2-NEXT: movdqa (%rdx,%rax), %xmm2 +; SSE2-NEXT: psubw %xmm0, %xmm2 +; SSE2-NEXT: pmullw %xmm1, %xmm2 +; SSE2-NEXT: movq %xmm2, (%rcx,%rax) +; SSE2-NEXT: pextrw $4, %xmm2, %edx +; SSE2-NEXT: movw %dx, 8(%rcx,%rax) +; SSE2-NEXT: incl -{{[0-9]+}}(%rsp) +; SSE2-NEXT: .LBB0_1: # %forcond +; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax +; SSE2-NEXT: jl .LBB0_2 +; SSE2-NEXT: # %bb.3: # %afterfor +; SSE2-NEXT: retq +; +; SSE41-LABEL: update: +; SSE41: # %bb.0: # %entry +; SSE41-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movl %edx, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movq {{.*}}(%rip), %rax +; SSE41-NEXT: movq %rax, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movw $0, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movl $0, -{{[0-9]+}}(%rsp) +; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <271,271,271,271,271,u,u,u> +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <2,4,2,2,2,u,u,u> +; SSE41-NEXT: jmp .LBB0_1 +; SSE41-NEXT: .p2align 4, 0x90 +; SSE41-NEXT: .LBB0_2: # %forbody +; SSE41-NEXT: # in Loop: Header=BB0_1 Depth=1 +; SSE41-NEXT: movslq -{{[0-9]+}}(%rsp), %rax +; SSE41-NEXT: movq -{{[0-9]+}}(%rsp), %rcx +; SSE41-NEXT: shlq $4, %rax +; SSE41-NEXT: movq -{{[0-9]+}}(%rsp), %rdx +; SSE41-NEXT: movdqa (%rdx,%rax), %xmm2 +; SSE41-NEXT: psubw %xmm0, %xmm2 +; SSE41-NEXT: pmullw %xmm1, %xmm2 +; SSE41-NEXT: pextrw $4, %xmm2, 8(%rcx,%rax) +; SSE41-NEXT: movq %xmm2, (%rcx,%rax) +; SSE41-NEXT: incl -{{[0-9]+}}(%rsp) +; SSE41-NEXT: .LBB0_1: # %forcond +; SSE41-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE41-NEXT: movl -{{[0-9]+}}(%rsp), %eax +; SSE41-NEXT: cmpl -{{[0-9]+}}(%rsp), %eax +; SSE41-NEXT: jl .LBB0_2 +; SSE41-NEXT: # %bb.3: # %afterfor +; SSE41-NEXT: retq entry: %dst.addr = alloca <5 x i16>* %src.addr = alloca <5 x i16>*