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AMDGPU : Fix SAD related instruction LIT tests function atttibute issues.

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Differential Revision: http://reviews.llvm.org/D23133

llvm-svn: 278360
This commit is contained in:
Wei Ding 2016-08-11 17:14:17 +00:00
parent 51ce2b263f
commit 1424300899
7 changed files with 14 additions and 21 deletions
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5
test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.mqsad.pk.u16.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8:
; GCN: v_mqsad_pk_u16_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_mqsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_mqsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.mqsad.pk.u16.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_mqsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_mqsad_pk_u16_u8_non_immediate:
; GCN: v_mqsad_pk_u16_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_mqsad_pk_u16_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_mqsad_pk_u16_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.mqsad.pk.u16.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.mqsad.u32.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_mqsad_u32_u8:
; GCN: v_mqsad_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_mqsad_u32_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_mqsad_u32_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.mqsad.u32.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_mqsad_u32_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_mqsad_u32_u8_non_immediate:
; GCN: v_mqsad_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_mqsad_u32_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_mqsad_u32_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.mqsad.u32.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.msad.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_msad_u8:
; GCN: v_msad_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_msad_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_msad_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.msad.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_msad_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_msad_u8_non_immediate:
; GCN: v_msad_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_msad_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_msad_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.msad.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.qsad.pk.u16.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_qsad_pk_u16_u8:
; GCN: v_qsad_pk_u16_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_qsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_qsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.qsad.pk.u16.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_qsad_pk_u16_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_qsad_pk_u16_u8_non_immediate:
; GCN: v_qsad_pk_u16_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_qsad_pk_u16_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_qsad_pk_u16_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.qsad.pk.u16.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.sad.hi.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_sad_hi_u8:
; GCN: v_sad_hi_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_hi_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_sad_hi_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.sad.hi.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_sad_hi_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_sad_hi_u8_non_immediate:
; GCN: v_sad_hi_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_hi_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_sad_hi_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.sad.hi.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #0 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.sad.u16(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_sad_u16:
; GCN: v_sad_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_u16(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_sad_u16(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.sad.u16(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_sad_u16(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_sad_u16_non_immediate:
; GCN: v_sad_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_u16_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_sad_u16_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.sad.u16(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #0 = { nounwind }

5
test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
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@ -5,7 +5,7 @@ declare i32 @llvm.amdgcn.sad.u8(i32, i32, i32) #0
; GCN-LABEL: {{^}}v_sad_u8:
; GCN: v_sad_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_u8(i32 addrspace(1)* %out, i32 %src) #1 {
define void @v_sad_u8(i32 addrspace(1)* %out, i32 %src) {
%result= call i32 @llvm.amdgcn.sad.u8(i32 %src, i32 100, i32 100) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
@ -13,11 +13,10 @@ define void @v_sad_u8(i32 addrspace(1)* %out, i32 %src) #1 {
; GCN-LABEL: {{^}}v_sad_u8_non_immediate:
; GCN: v_sad_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @v_sad_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) #1 {
define void @v_sad_u8_non_immediate(i32 addrspace(1)* %out, i32 %src, i32 %a, i32 %b) {
%result= call i32 @llvm.amdgcn.sad.u8(i32 %src, i32 %a, i32 %b) #0
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
attributes #0 = { nounwind readnone }
attributes #0 = { nounwind }