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[InstCombine] use 'match' to handle vectors and simplify code

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This is another step towards completely removing the fake 
binop queries for not/neg/fneg.

llvm-svn: 345036
This commit is contained in:
Sanjay Patel 2018-10-23 15:05:12 +00:00
parent e4ec3df7e4
commit 1425492643
3 changed files with 6 additions and 7 deletions
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5
lib/Transforms/InstCombine/InstCombineSelect.cpp
View File

@ -1989,8 +1989,9 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
} }
} }
if (BinaryOperator::isNot(CondVal)) { Value *NotCond;
SI.setOperand(0, BinaryOperator::getNotArgument(CondVal)); if (match(CondVal, m_Not(m_Value(NotCond)))) {
SI.setOperand(0, NotCond);
SI.setOperand(1, FalseVal); SI.setOperand(1, FalseVal);
SI.setOperand(2, TrueVal); SI.setOperand(2, TrueVal);
SI.swapProfMetadata(); SI.swapProfMetadata();

5
test/Transforms/InstCombine/select_meta.ll
View File

@ -322,13 +322,12 @@ define <2 x i32> @not_cond_vec(<2 x i1> %c, <2 x i32> %tv, <2 x i32> %fv) {
ret <2 x i32> %r ret <2 x i32> %r
} }
; FIXME: Should match vector 'not' with undef element. After that... ; Should match vector 'not' with undef element.
; The condition is inverted, and the select ops are swapped. The metadata should be swapped. ; The condition is inverted, and the select ops are swapped. The metadata should be swapped.
define <2 x i32> @not_cond_vec_undef(<2 x i1> %c, <2 x i32> %tv, <2 x i32> %fv) { define <2 x i32> @not_cond_vec_undef(<2 x i1> %c, <2 x i32> %tv, <2 x i32> %fv) {
; CHECK-LABEL: @not_cond_vec_undef( ; CHECK-LABEL: @not_cond_vec_undef(
; CHECK-NEXT: [[NOTC:%.*]] = xor <2 x i1> [[C:%.*]], <i1 undef, i1 true> ; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C:%.*]], <2 x i32> [[FV:%.*]], <2 x i32> [[TV:%.*]], !prof ![[$MD3]]
; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[NOTC]], <2 x i32> [[TV:%.*]], <2 x i32> [[FV:%.*]], !prof ![[$MD1]]
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%notc = xor <2 x i1> %c, <i1 undef, i1 true> %notc = xor <2 x i1> %c, <i1 undef, i1 true>

3
test/Transforms/LoopVectorize/invariant-store-vectorization.ll
View File

@ -293,8 +293,7 @@ for.end: ; preds = %for.body
; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT5]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT5]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i1> undef, i1 [[CMP]], i32 3 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i1> undef, i1 [[CMP]], i32 3
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> undef, i32 [[K]], i32 3 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> undef, i32 [[K]], i32 3
; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i1> [[TMP2]], <i1 undef, i1 undef, i1 undef, i1 true> ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[BROADCAST_SPLAT6]], <4 x i32> [[TMP3]]
; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[TMP3]], <4 x i32> [[BROADCAST_SPLAT6]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body: ; CHECK: vector.body: