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[Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.

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llvm-svn: 226194
This commit is contained in:
Colin LeMahieu 2015-01-15 19:28:32 +00:00
parent 5cf742495d
commit 14474ecfe7
4 changed files with 49 additions and 47 deletions
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6
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -355,11 +355,11 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID)
case Intrinsic::hexagon_C2_muxii:
return Hexagon::C2_muxii;
case Intrinsic::hexagon_C2_vmux:
return Hexagon::VMUX_prr64;
return Hexagon::C2_vmux;
case Intrinsic::hexagon_S2_valignrb:
return Hexagon::VALIGN_rrp;
return Hexagon::S2_valignrb;
case Intrinsic::hexagon_S2_vsplicerb:
return Hexagon::VSPLICE_rrp;
return Hexagon::S2_vsplicerb;
}
}

82
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -30,6 +30,20 @@ def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
def LoReg: OutPatFrag<(ops node:$Rs),
(EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
// SDNode for converting immediate C to C-1.
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue();
return XformSToSM1Imm(imm);
}]>;
// SDNode for converting immediate C to C-1.
def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
uint32_t imm = N->getZExtValue();
return XformUToUM1Imm(imm);
}]>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
@ -799,14 +813,6 @@ def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
// Mux.
def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
DoubleRegs:$src2,
DoubleRegs:$src3),
"$dst = vmux($src1, $src2, $src3)",
[]>;
//===----------------------------------------------------------------------===//
// ALU32/PERM -
//===----------------------------------------------------------------------===//
@ -816,28 +822,6 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
// ALU32/PRED +
//===----------------------------------------------------------------------===//
// SDNode for converting immediate C to C-1.
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
int32_t imm = N->getSExtValue();
return XformSToSM1Imm(imm);
}]>;
// SDNode for converting immediate C to C-1.
def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
uint32_t imm = N->getZExtValue();
return XformUToUM1Imm(imm);
}]>;
def CTLZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
"$dst = cl0($src1)",
[(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
def CTTZ64_rr : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
"$dst = ct0($src1)",
[(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
//===----------------------------------------------------------------------===//
// ALU32/PRED -
//===----------------------------------------------------------------------===//
@ -1253,18 +1237,6 @@ def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
let Inst{4-0} = Rd;
}
def VALIGN_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2,
PredRegs:$src3),
"$dst = valignb($src1, $src2, $src3)",
[]>;
def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2,
PredRegs:$src3),
"$dst = vspliceb($src1, $src2, $src3)",
[]>;
// User control register transfer.
//===----------------------------------------------------------------------===//
// CR -
@ -4941,6 +4913,32 @@ class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
let isCodeGenOnly = 0 in
def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
let hasSideEffects = 0 in
class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
: SInst < (outs DoubleRegs:$Rdd),
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
"$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
[], "", S_3op_tc_1_SLOT23 > {
bits<5> Rdd;
bits<5> Rss;
bits<5> Rtt;
bits<2> Pu;
let IClass = 0b1100;
let Inst{27-24} = 0b0010;
let Inst{23-21} = MajOp;
let Inst{20-16} = !if (SwapOps, Rtt, Rss);
let Inst{12-8} = !if (SwapOps, Rss, Rtt);
let Inst{6-5} = Pu;
let Inst{4-0} = Rdd;
}
let isCodeGenOnly = 0 in {
def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
}
//===----------------------------------------------------------------------===//
// Template class used by vector shift, vector rotate, vector neg,
// 32-bit shift, 64-bit shifts, etc.

4
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -3725,11 +3725,11 @@ def STriw_offset_ext_V4 : STInst<(outs),
Requires<[HasV4T]>;
def : Pat<(i64 (ctlz (i64 DoubleRegs:$src1))),
(i64 (A4_combineir (i32 0), (i32 (CTLZ64_rr DoubleRegs:$src1))))>,
(i64 (A4_combineir (i32 0), (i32 (S2_cl0p DoubleRegs:$src1))))>,
Requires<[HasV4T]>;
def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))),
(i64 (A4_combineir (i32 0), (i32 (CTTZ64_rr DoubleRegs:$src1))))>,
(i64 (A4_combineir (i32 0), (i32 (S2_ct0p DoubleRegs:$src1))))>,
Requires<[HasV4T]>;

4
test/MC/Disassembler/Hexagon/xtype_perm.txt
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@ -12,3 +12,7 @@
# CHECK: r17 = satb(r21)
0xf1 0xc0 0x95 0x8c
# CHECK: r17 = swiz(r21)
0x70 0xd4 0x1e 0xc2
# CHECK: r17:16 = valignb(r21:20, r31:30, p3)
0x70 0xde 0x94 0xc2
# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)