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Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."

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I thought this might help with another optimization I was
thinking about, but I don't think it will. So it just wastes
compile time calling computeKnownBits for no benefit.

This reverts commit 81b2f95971edd47a0057ac4a77b674d7ea620c01.
This commit is contained in:
Craig Topper 2021-06-27 10:32:48 -07:00
parent b0bb011472
commit 14af611f66
14 changed files with 551 additions and 551 deletions
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4
lib/Target/RISCV/RISCVInstrInfo.td
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@ -1262,11 +1262,11 @@ def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32),
(SUBW GPR:$rs1, GPR:$rs2)>;
def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
(SLLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (srl (zexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
def : Pat<(i64 (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
(SRLIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
def : Pat<(i64 (sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
(SRAIW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;

2
test/CodeGen/RISCV/alu8.ll
View File

@ -124,7 +124,7 @@ define i8 @srli(i8 %a) nounwind {
; RV64I-LABEL: srli:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 192
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
%1 = lshr i8 %a, 6
ret i8 %1

4
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
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@ -499,9 +499,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1

2
test/CodeGen/RISCV/copysign-casts.ll
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@ -357,7 +357,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 31
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a1, a1, 16
; RV64I-NEXT: srli a1, a1, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;

12
test/CodeGen/RISCV/div.ll
View File

@ -276,7 +276,7 @@ define i8 @udiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: addi a1, zero, 205
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 10
; RV64IM-NEXT: srli a0, a0, 10
; RV64IM-NEXT: ret
%1 = udiv i8 %a, 5
ret i8 %1
@ -298,13 +298,13 @@ define i8 @udiv8_pow2(i8 %a) nounwind {
; RV64I-LABEL: udiv8_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 248
; RV64I-NEXT: srliw a0, a0, 3
; RV64I-NEXT: srli a0, a0, 3
; RV64I-NEXT: ret
;
; RV64IM-LABEL: udiv8_pow2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: andi a0, a0, 248
; RV64IM-NEXT: srliw a0, a0, 3
; RV64IM-NEXT: srli a0, a0, 3
; RV64IM-NEXT: ret
%1 = udiv i8 %a, 8
ret i8 %1
@ -404,7 +404,7 @@ define i16 @udiv16_constant(i16 %a) nounwind {
; RV64IM-NEXT: lui a1, 13
; RV64IM-NEXT: addiw a1, a1, -819
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 18
; RV64IM-NEXT: srli a0, a0, 18
; RV64IM-NEXT: ret
%1 = udiv i16 %a, 5
ret i16 %1
@ -786,7 +786,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: addi a1, zero, 103
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: sraiw a1, a0, 9
; RV64IM-NEXT: srai a1, a0, 9
; RV64IM-NEXT: srli a0, a0, 15
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: add a0, a1, a0
@ -935,7 +935,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: sraiw a1, a0, 17
; RV64IM-NEXT: srai a1, a0, 17
; RV64IM-NEXT: srli a0, a0, 31
; RV64IM-NEXT: andi a0, a0, 1
; RV64IM-NEXT: add a0, a1, a0

10
test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
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@ -1529,7 +1529,7 @@ define i32 @aext_srliw_sext(i32 signext %a) nounwind {
define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: aext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 3
; RV64I-NEXT: srli a0, a0, 3
; RV64I-NEXT: ret
%1 = lshr i32 %a, 3
ret i32 %1
@ -1556,7 +1556,7 @@ define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: sext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
%1 = lshr i32 %a, 6
ret i32 %1
@ -1583,7 +1583,7 @@ define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: zext_srliw_zext:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a0, a0, 9
; RV64I-NEXT: srli a0, a0, 9
; RV64I-NEXT: ret
%1 = lshr i32 %a, 9
ret i32 %1
@ -1603,7 +1603,7 @@ define i32 @aext_sraiw_aext(i32 %a) nounwind {
define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: aext_sraiw_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 2
; RV64I-NEXT: srai a0, a0, 2
; RV64I-NEXT: ret
%1 = ashr i32 %a, 2
ret i32 %1
@ -1630,7 +1630,7 @@ define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: sext_sraiw_sext:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a0, a0, 5
; RV64I-NEXT: srai a0, a0, 5
; RV64I-NEXT: ret
%1 = ashr i32 %a, 5
ret i32 %1

22
test/CodeGen/RISCV/rv64zbb-zbp.ll
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@ -614,25 +614,25 @@ define i8 @srli_i8(i8 %a) nounwind {
; RV64I-LABEL: srli_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 192
; RV64I-NEXT: srliw a0, a0, 6
; RV64I-NEXT: srli a0, a0, 6
; RV64I-NEXT: ret
;
; RV64IB-LABEL: srli_i8:
; RV64IB: # %bb.0:
; RV64IB-NEXT: andi a0, a0, 192
; RV64IB-NEXT: srliw a0, a0, 6
; RV64IB-NEXT: srli a0, a0, 6
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srli_i8:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: andi a0, a0, 192
; RV64IBB-NEXT: srliw a0, a0, 6
; RV64IBB-NEXT: srli a0, a0, 6
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srli_i8:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: andi a0, a0, 192
; RV64IBP-NEXT: srliw a0, a0, 6
; RV64IBP-NEXT: srli a0, a0, 6
; RV64IBP-NEXT: ret
%1 = lshr i8 %a, 6
ret i8 %1
@ -648,13 +648,13 @@ define i8 @srai_i8(i8 %a) nounwind {
; RV64IB-LABEL: srai_i8:
; RV64IB: # %bb.0:
; RV64IB-NEXT: sext.b a0, a0
; RV64IB-NEXT: sraiw a0, a0, 5
; RV64IB-NEXT: srai a0, a0, 5
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srai_i8:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: sext.b a0, a0
; RV64IBB-NEXT: sraiw a0, a0, 5
; RV64IBB-NEXT: srai a0, a0, 5
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srai_i8:
@ -676,19 +676,19 @@ define i16 @srli_i16(i16 %a) nounwind {
; RV64IB-LABEL: srli_i16:
; RV64IB: # %bb.0:
; RV64IB-NEXT: zext.h a0, a0
; RV64IB-NEXT: srliw a0, a0, 6
; RV64IB-NEXT: srli a0, a0, 6
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srli_i16:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: zext.h a0, a0
; RV64IBB-NEXT: srliw a0, a0, 6
; RV64IBB-NEXT: srli a0, a0, 6
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srli_i16:
; RV64IBP: # %bb.0:
; RV64IBP-NEXT: zext.h a0, a0
; RV64IBP-NEXT: srliw a0, a0, 6
; RV64IBP-NEXT: srli a0, a0, 6
; RV64IBP-NEXT: ret
%1 = lshr i16 %a, 6
ret i16 %1
@ -704,13 +704,13 @@ define i16 @srai_i16(i16 %a) nounwind {
; RV64IB-LABEL: srai_i16:
; RV64IB: # %bb.0:
; RV64IB-NEXT: sext.h a0, a0
; RV64IB-NEXT: sraiw a0, a0, 9
; RV64IB-NEXT: srai a0, a0, 9
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: srai_i16:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: sext.h a0, a0
; RV64IBB-NEXT: sraiw a0, a0, 9
; RV64IBB-NEXT: srai a0, a0, 9
; RV64IBB-NEXT: ret
;
; RV64IBP-LABEL: srai_i16:

24
test/CodeGen/RISCV/rv64zbb.ll
View File

@ -19,9 +19,9 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
@ -105,9 +105,9 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
@ -202,9 +202,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
@ -295,9 +295,9 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: srliw a1, s0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
@ -395,11 +395,11 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB4_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 2
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
@ -1016,7 +1016,7 @@ define signext i32 @ctpop_i32_load(i32* %p) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lwu a0, 0(a0)
; RV64I-NEXT: srliw a1, a0, 1
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: and a1, a1, a2

28
test/CodeGen/RISCV/rv64zbp.ll
View File

@ -2669,7 +2669,7 @@ declare i16 @llvm.bswap.i16(i16)
define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind {
; RV64I-LABEL: bswap_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 16
@ -2812,19 +2812,19 @@ declare i8 @llvm.bitreverse.i8(i8)
define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
; RV64I-LABEL: bitreverse_i8:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 4
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: andi a1, a0, 51
; RV64I-NEXT: slli a1, a1, 2
; RV64I-NEXT: andi a0, a0, 204
; RV64I-NEXT: srliw a0, a0, 2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: andi a1, a0, 85
; RV64I-NEXT: slli a1, a1, 1
; RV64I-NEXT: andi a0, a0, 170
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -2846,7 +2846,7 @@ declare i16 @llvm.bitreverse.i16(i16)
define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
; RV64I-LABEL: bitreverse_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a0, 8
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: slli a0, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 1
@ -2856,7 +2856,7 @@ define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
; RV64I-NEXT: lui a2, 15
; RV64I-NEXT: addiw a2, a2, 240
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 4
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 3
; RV64I-NEXT: addiw a1, a1, 819
@ -2865,7 +2865,7 @@ define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
; RV64I-NEXT: lui a2, 13
; RV64I-NEXT: addiw a2, a2, -820
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 5
; RV64I-NEXT: addiw a1, a1, 1365
@ -2874,7 +2874,7 @@ define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
; RV64I-NEXT: lui a2, 11
; RV64I-NEXT: addiw a2, a2, -1366
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
@ -2917,7 +2917,7 @@ define signext i32 @bitreverse_i32(i32 signext %a) nounwind {
; RV64I-NEXT: slli a2, a2, 12
; RV64I-NEXT: addi a2, a2, 240
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 4
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
@ -2926,7 +2926,7 @@ define signext i32 @bitreverse_i32(i32 signext %a) nounwind {
; RV64I-NEXT: lui a2, 838861
; RV64I-NEXT: addiw a2, a2, -820
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: srliw a0, a0, 2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365
@ -2978,7 +2978,7 @@ define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, 240
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srliw a0, a0, 4
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 209715
; RV64I-NEXT: addiw a2, a2, 819
@ -2987,7 +2987,7 @@ define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
; RV64I-NEXT: lui a3, 838861
; RV64I-NEXT: addiw a3, a3, -820
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srliw a0, a0, 2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
@ -3221,7 +3221,7 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: addi a3, a3, 240
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srliw a0, a0, 4
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
@ -3230,7 +3230,7 @@ define i32 @bitreverse_bswap_i32(i32 %a) {
; RV64I-NEXT: lui a3, 838861
; RV64I-NEXT: addiw a3, a3, -820
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: srliw a0, a0, 2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw a1, a1, 1365

960
test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
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File diff suppressed because it is too large Load Diff

4
test/CodeGen/RISCV/urem-lkk.ll
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@ -56,7 +56,7 @@ define i32 @fold_urem_positive_odd(i32 %x) nounwind {
; RV64IM-NEXT: sub a2, a0, a1
; RV64IM-NEXT: srliw a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srliw a1, a1, 6
; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
@ -189,7 +189,7 @@ define i32 @combine_urem_udiv(i32 %x) nounwind {
; RV64IM-NEXT: sub a2, a0, a1
; RV64IM-NEXT: srliw a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srliw a1, a1, 6
; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a2, a1, a2
; RV64IM-NEXT: sub a0, a0, a2

10
test/CodeGen/RISCV/urem-seteq-illegal-types.ll
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@ -119,7 +119,7 @@ define i1 @test_urem_even(i27 %X) nounwind {
; RV64-NEXT: lui a2, 32768
; RV64-NEXT: addiw a3, a2, -2
; RV64-NEXT: and a0, a0, a3
; RV64-NEXT: srliw a0, a0, 1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: addiw a1, a2, -1
; RV64-NEXT: and a0, a0, a1
@ -157,7 +157,7 @@ define i1 @test_urem_even(i27 %X) nounwind {
; RV64M-NEXT: lui a2, 32768
; RV64M-NEXT: addiw a3, a2, -2
; RV64M-NEXT: and a0, a0, a3
; RV64M-NEXT: srliw a0, a0, 1
; RV64M-NEXT: srli a0, a0, 1
; RV64M-NEXT: or a0, a0, a1
; RV64M-NEXT: addiw a1, a2, -1
; RV64M-NEXT: and a0, a0, a1
@ -193,7 +193,7 @@ define i1 @test_urem_even(i27 %X) nounwind {
; RV64MV-NEXT: lui a2, 32768
; RV64MV-NEXT: addiw a3, a2, -2
; RV64MV-NEXT: and a0, a0, a3
; RV64MV-NEXT: srliw a0, a0, 1
; RV64MV-NEXT: srli a0, a0, 1
; RV64MV-NEXT: or a0, a0, a1
; RV64MV-NEXT: addiw a1, a2, -1
; RV64MV-NEXT: and a0, a0, a1
@ -419,7 +419,7 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: slli a1, a0, 10
; RV64-NEXT: andi a0, a0, 2046
; RV64-NEXT: srliw a0, a0, 1
; RV64-NEXT: srli a0, a0, 1
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: addi a1, zero, 341
@ -518,7 +518,7 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64M-NEXT: mul a1, a1, a4
; RV64M-NEXT: slli a4, a1, 10
; RV64M-NEXT: andi a1, a1, 2046
; RV64M-NEXT: srliw a1, a1, 1
; RV64M-NEXT: srli a1, a1, 1
; RV64M-NEXT: or a1, a1, a4
; RV64M-NEXT: andi a1, a1, 2047
; RV64M-NEXT: addi a4, zero, 341

16
test/CodeGen/RISCV/urem-vector-lkk.ll
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@ -164,7 +164,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV64IM-NEXT: addi a5, zero, 95
; RV64IM-NEXT: mul a2, a2, a5
; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: srliw a2, a4, 2
; RV64IM-NEXT: srli a2, a4, 2
; RV64IM-NEXT: lui a5, 264
; RV64IM-NEXT: addiw a5, a5, 1057
; RV64IM-NEXT: slli a5, a5, 15
@ -174,11 +174,11 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV64IM-NEXT: slli a5, a5, 12
; RV64IM-NEXT: addi a5, a5, 133
; RV64IM-NEXT: mulhu a2, a2, a5
; RV64IM-NEXT: srliw a2, a2, 3
; RV64IM-NEXT: srli a2, a2, 3
; RV64IM-NEXT: addi a5, zero, 124
; RV64IM-NEXT: mul a2, a2, a5
; RV64IM-NEXT: sub a2, a4, a2
; RV64IM-NEXT: srliw a4, a3, 1
; RV64IM-NEXT: srli a4, a3, 1
; RV64IM-NEXT: lui a5, 2675
; RV64IM-NEXT: addiw a5, a5, -251
; RV64IM-NEXT: slli a5, a5, 13
@ -188,7 +188,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV64IM-NEXT: slli a5, a5, 13
; RV64IM-NEXT: addi a5, a5, 1505
; RV64IM-NEXT: mulhu a4, a4, a5
; RV64IM-NEXT: srliw a4, a4, 4
; RV64IM-NEXT: srli a4, a4, 4
; RV64IM-NEXT: addi a5, zero, 98
; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a3, a3, a4
@ -201,7 +201,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: addi a4, a4, 1213
; RV64IM-NEXT: mulhu a4, a6, a4
; RV64IM-NEXT: srliw a4, a4, 7
; RV64IM-NEXT: srli a4, a4, 7
; RV64IM-NEXT: addi a5, zero, 1003
; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a4, a6, a4
@ -902,7 +902,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV64IM-NEXT: addi a5, zero, 23
; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a1, a1, a4
; RV64IM-NEXT: srliw a4, a3, 1
; RV64IM-NEXT: srli a4, a3, 1
; RV64IM-NEXT: lui a5, 6413
; RV64IM-NEXT: addiw a5, a5, 1265
; RV64IM-NEXT: slli a5, a5, 13
@ -912,7 +912,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV64IM-NEXT: slli a5, a5, 12
; RV64IM-NEXT: addi a5, a5, 965
; RV64IM-NEXT: mulhu a4, a4, a5
; RV64IM-NEXT: srliw a4, a4, 7
; RV64IM-NEXT: srli a4, a4, 7
; RV64IM-NEXT: addi a5, zero, 654
; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a3, a3, a4
@ -925,7 +925,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV64IM-NEXT: slli a4, a4, 12
; RV64IM-NEXT: addi a4, a4, -179
; RV64IM-NEXT: mulhu a4, a2, a4
; RV64IM-NEXT: srliw a4, a4, 12
; RV64IM-NEXT: srli a4, a4, 12
; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a4, a4, a5

4
test/CodeGen/RISCV/vec3-setcc-crash.ll
View File

@ -70,7 +70,7 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV64-NEXT: mv a2, zero
; RV64-NEXT: j .LBB0_5
; RV64-NEXT: .LBB0_4:
; RV64-NEXT: srliw a2, a2, 8
; RV64-NEXT: srli a2, a2, 8
; RV64-NEXT: .LBB0_5:
; RV64-NEXT: slli a2, a2, 8
; RV64-NEXT: or a2, a5, a2
@ -79,7 +79,7 @@ define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV64-NEXT: mv a0, zero
; RV64-NEXT: j .LBB0_8
; RV64-NEXT: .LBB0_7:
; RV64-NEXT: srliw a0, a0, 16
; RV64-NEXT: srli a0, a0, 16
; RV64-NEXT: .LBB0_8:
; RV64-NEXT: sb a0, 2(a1)
; RV64-NEXT: sh a2, 0(a1)