RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity

Don't add or sub zero to sp.

Browse Source 
llvm-svn: 33142
This commit is contained in:
Lauro Ramos Venancio 2007-01-12 20:52:27 +00:00
parent 97e120a71c
commit 14cf9f2c03
2 changed files with 20 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -206,9 +206,11 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MFI->setStackSize(NumBytes);
//sub sp, sp, #NumBytes
splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
ARM::R13, NumBytes);
if (NumBytes) {
//sub sp, sp, #NumBytes
splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
ARM::R13, NumBytes);
}
if (HasFP) {
@ -234,9 +236,11 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
}
//add sp, sp, #NumBytes
splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
ARM::R13, NumBytes);
if (NumBytes){
//add sp, sp, #NumBytes
splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
ARM::R13, NumBytes);
}
}

10
test/Regression/CodeGen/ARM/spaddsub.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -f -march=arm -o %t.s &&
; RUN: not grep "add r13, r13, #0" < %t.s &&
; RUN: not grep "sub r13, r13, #0" < %t.s
int %f() {
entry:
ret int 1
}