From 14f985bea0cb0035d1342d84a39a066dfce7d99b Mon Sep 17 00:00:00 2001 From: Hrvoje Varga Date: Thu, 15 Oct 2015 08:11:50 +0000 Subject: [PATCH] [mips][microMIPS] Implement LLE and SCE instructions Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379 --- .../Mips/Disassembler/MipsDisassembler.cpp | 3 +++ lib/Target/Mips/MicroMipsInstrFormats.td | 16 ++++++++++++++++ lib/Target/Mips/MicroMipsInstrInfo.td | 18 ++++++++++++++++++ .../Mips/micromips32r3/valid-el.txt | 2 ++ .../Disassembler/Mips/micromips32r3/valid.txt | 2 ++ test/MC/Mips/micromips-control-instructions.s | 6 ++++++ 6 files changed, 47 insertions(+) diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 27eb399ba96..79268e5e184 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1411,6 +1411,9 @@ static DecodeStatus DecodeMemMMImm9(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + if (Inst.getOpcode() == Mips::SCE_MM) + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createImm(Offset)); diff --git a/lib/Target/Mips/MicroMipsInstrFormats.td b/lib/Target/Mips/MicroMipsInstrFormats.td index eb3456c2d74..e2cf4ca2f4b 100644 --- a/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/lib/Target/Mips/MicroMipsInstrFormats.td @@ -687,6 +687,22 @@ class LL_FM_MM funct> { let Inst{11-0} = addr{11-0}; } +class LLE_FM_MM funct> { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = 0x18; + let Inst{25-21} = rt; + let Inst{20-16} = base; + let Inst{15-12} = funct; + let Inst{11-9} = 0x6; + let Inst{8-0} = offset; +} + class ADDS_FM_MM fmt, bits<8> funct> : MMArch { bits<5> ft; bits<5> fs; diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index a858a9ec908..cf4e2957ff5 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -268,6 +268,13 @@ class LLBaseMM : let mayLoad = 1; } +class LLEBaseMM : + InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMemMMImm9"; + let mayLoad = 1; +} + class SCBaseMM : InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr), !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { @@ -276,6 +283,14 @@ class SCBaseMM : let Constraints = "$rt = $dst"; } +class SCEBaseMM : + InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMemMMImm9"; + let mayStore = 1; + let Constraints = "$rt = $dst"; +} + class LoadMM : InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), @@ -901,6 +916,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>; + def LLE_MM : LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>; + def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>; + let DecoderMethod = "DecodeCacheOpMM" in { def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>, CACHE_PREF_FM_MM<0x08, 0x6>; diff --git a/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt index f8df6399ad9..d6c7de4e3a5 100644 --- a/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ b/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -187,3 +187,5 @@ 0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3) 0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3) 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) +0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) +0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) diff --git a/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/test/MC/Disassembler/Mips/micromips32r3/valid.txt index 76b02c3c4e6..030afb36723 100644 --- a/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ b/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -187,3 +187,5 @@ 0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3) 0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3) 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) +0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) +0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index 5e4d5c468b5..6c0dabaeec8 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -46,6 +46,8 @@ # CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0] # CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66] # CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64] +# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c] +# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -86,6 +88,8 @@ # CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05] # CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05] # CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02] +# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08] +# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08] sdbbp sdbbp 34 @@ -121,3 +125,5 @@ swle $24, 5($3) lwre $24, 5($3) lwle $24, 2($4) + lle $2, 8($4) + sce $2, 8($4)