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ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. llvm-svn: 135596
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@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
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// First, split out any predication code. Ignore mnemonics we know aren't
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// predicated but do have a carry-set and so weren't caught above.
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if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
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if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
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Mnemonic != "muls") {
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unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
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.Case("eq", ARMCC::EQ)
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.Case("ne", ARMCC::NE)
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@ -811,6 +811,20 @@ _func:
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@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
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@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
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@------------------------------------------------------------------------------
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@ MUL
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@------------------------------------------------------------------------------
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mul r5, r6, r7
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muls r5, r6, r7
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mulgt r5, r6, r7
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mulsle r5, r6, r7
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@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0]
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@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
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@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0]
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@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0]
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@------------------------------------------------------------------------------
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@ STM*
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@------------------------------------------------------------------------------
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