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[RISCV] Implement branch analysis
This is a prerequisite for the branch relaxation pass, and allows a number of optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work. Differential Revision: https://reviews.llvm.org/D40808 llvm-svn: 322222
This commit is contained in:
Alex Bradbury
parent
272abbd2f8
commit
1534210353
@ -95,3 +95,169 @@ void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
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.addImm(Lo12)
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.setMIFlag(Flag);
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}
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// The contents of values added to Cond are not examined outside of
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// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
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// push BranchOpcode, Reg1, Reg2.
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static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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Target = LastInst.getOperand(2).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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Cond.push_back(LastInst.getOperand(0));
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Cond.push_back(LastInst.getOperand(1));
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}
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static unsigned getOppositeBranchOpcode(int Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Unrecognized conditional branch");
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case RISCV::BEQ:
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return RISCV::BNE;
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case RISCV::BNE:
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return RISCV::BEQ;
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case RISCV::BLT:
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return RISCV::BGE;
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case RISCV::BGE:
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return RISCV::BLT;
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case RISCV::BLTU:
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return RISCV::BGEU;
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case RISCV::BGEU:
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return RISCV::BLTU;
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}
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}
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bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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Cond.clear();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end() || !isUnpredicatedTerminator(*I))
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return false;
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// Count the number of terminators and find the first unconditional or
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// indirect branch.
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MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
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int NumTerminators = 0;
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for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
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J++) {
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NumTerminators++;
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if (J->getDesc().isUnconditionalBranch() ||
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J->getDesc().isIndirectBranch()) {
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FirstUncondOrIndirectBr = J.getReverse();
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}
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}
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// If AllowModify is true, we can erase any terminators after
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// FirstUncondOrIndirectBR.
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if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
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while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
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std::next(FirstUncondOrIndirectBr)->eraseFromParent();
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NumTerminators--;
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}
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I = FirstUncondOrIndirectBr;
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}
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// We can't handle blocks that end in an indirect branch.
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if (I->getDesc().isIndirectBranch())
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return true;
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// We can't handle blocks with more than 2 terminators.
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if (NumTerminators > 2)
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return true;
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// Handle a single unconditional branch.
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if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
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TBB = I->getOperand(0).getMBB();
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return false;
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}
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// Handle a single conditional branch.
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if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
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parseCondBranch(*I, TBB, Cond);
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return false;
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}
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// Handle a conditional branch followed by an unconditional branch.
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if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
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I->getDesc().isUnconditionalBranch()) {
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parseCondBranch(*std::prev(I), TBB, Cond);
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FBB = I->getOperand(0).getMBB();
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return false;
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}
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// Otherwise, we can't handle this.
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return true;
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}
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unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "Code size not handled");
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (!I->getDesc().isUnconditionalBranch() &&
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!I->getDesc().isConditionalBranch())
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!I->getDesc().isConditionalBranch())
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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// Inserts a branch into the end of the specific MachineBasicBlock, returning
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// the number of instructions inserted.
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unsigned RISCVInstrInfo::insertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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assert(!BytesAdded && "Code size not handled.");
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 0) &&
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"RISCV branch conditions have two components!");
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// Unconditional branch.
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if (Cond.empty()) {
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BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
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return 1;
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}
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// Either a one or two-way conditional branch.
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unsigned Opc = Cond[0].getImm();
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BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
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// One-way conditional branch.
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if (!FBB)
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return 1;
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// Two-way conditional branch.
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BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
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return 2;
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}
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bool RISCVInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 3) && "Invalid branch condition!");
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Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
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return false;
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}
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@ -46,6 +46,22 @@ public:
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void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &dl,
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int *BytesAdded = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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};
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}
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#endif
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91
test/CodeGen/RISCV/analyze-branch.ll
Normal file
91
test/CodeGen/RISCV/analyze-branch.ll
Normal file
@ -0,0 +1,91 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; This test checks that LLVM can do basic stripping and reapplying of branches
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; to basic blocks.
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declare void @test_true()
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declare void @test_false()
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; !0 corresponds to a branch being taken, !1 to not being takne.
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!0 = !{!"branch_weights", i32 64, i32 4}
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!1 = !{!"branch_weights", i32 4, i32 64}
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define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
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; RV32I-LABEL: test_bcc_fallthrough_taken:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: addi a1, zero, 42
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; RV32I-NEXT: bne a0, a1, .LBB0_3
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; RV32I-NEXT: # %bb.1: # %true
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; RV32I-NEXT: lui a0, %hi(test_true)
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; RV32I-NEXT: addi a0, a0, %lo(test_true)
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; RV32I-NEXT: .LBB0_2: # %true
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; RV32I-NEXT: jalr a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB0_3: # %false
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; RV32I-NEXT: lui a0, %hi(test_false)
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; RV32I-NEXT: addi a0, a0, %lo(test_false)
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; RV32I-NEXT: j .LBB0_2
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%tst = icmp eq i32 %in, 42
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br i1 %tst, label %true, label %false, !prof !0
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; Expected layout order is: Entry, TrueBlock, FalseBlock
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; Entry->TrueBlock is the common path, which should be taken whenever the
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; conditional branch is false.
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true:
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call void @test_true()
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ret void
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false:
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call void @test_false()
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ret void
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}
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define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
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; RV32I-LABEL: test_bcc_fallthrough_nottaken:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: addi a1, zero, 42
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; RV32I-NEXT: beq a0, a1, .LBB1_1
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; RV32I-NEXT: # %bb.3: # %false
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; RV32I-NEXT: lui a0, %hi(test_false)
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; RV32I-NEXT: addi a0, a0, %lo(test_false)
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; RV32I-NEXT: .LBB1_2: # %true
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; RV32I-NEXT: jalr a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB1_1: # %true
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; RV32I-NEXT: lui a0, %hi(test_true)
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; RV32I-NEXT: addi a0, a0, %lo(test_true)
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; RV32I-NEXT: j .LBB1_2
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%tst = icmp eq i32 %in, 42
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br i1 %tst, label %true, label %false, !prof !1
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; Expected layout order is: Entry, FalseBlock, TrueBlock
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; Entry->FalseBlock is the common path, which should be taken whenever the
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; conditional branch is false
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true:
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call void @test_true()
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ret void
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false:
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call void @test_false()
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ret void
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}
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; TODO: how can we expand the coverage of the branch analysis functions?
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@ -11,49 +11,38 @@ define void @foo(i32 %a, i32 *%b, i1 %c) {
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: beq a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_1
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; RV32I-NEXT: .LBB0_1: # %test2
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; RV32I-NEXT: # %bb.1: # %test2
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bne a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_2
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; RV32I-NEXT: .LBB0_2: # %test3
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; RV32I-NEXT: # %bb.2: # %test3
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_3
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; RV32I-NEXT: .LBB0_3: # %test4
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; RV32I-NEXT: # %bb.3: # %test4
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_4
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; RV32I-NEXT: .LBB0_4: # %test5
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; RV32I-NEXT: # %bb.4: # %test5
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_5
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; RV32I-NEXT: .LBB0_5: # %test6
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; RV32I-NEXT: # %bb.5: # %test6
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_6
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; RV32I-NEXT: .LBB0_6: # %test7
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; RV32I-NEXT: # %bb.6: # %test7
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_7
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; RV32I-NEXT: .LBB0_7: # %test8
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; RV32I-NEXT: # %bb.7: # %test8
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_8
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; RV32I-NEXT: .LBB0_8: # %test9
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; RV32I-NEXT: # %bb.8: # %test9
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_9
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; RV32I-NEXT: .LBB0_9: # %test10
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; RV32I-NEXT: # %bb.9: # %test10
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_10
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; RV32I-NEXT: .LBB0_10: # %test11
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; RV32I-NEXT: # %bb.10: # %test11
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: andi a0, a2, 1
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; RV32I-NEXT: bnez a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_11
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; RV32I-NEXT: .LBB0_11: # %test12
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; RV32I-NEXT: # %bb.11: # %test12
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: .LBB0_12: # %end
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; RV32I-NEXT: lw s0, 8(sp)
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@ -107,15 +107,12 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: addi a0, zero, 8
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; RV32I-NEXT: andi a2, a1, 255
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; RV32I-NEXT: beqz a2, .LBB3_2
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; RV32I-NEXT: j .LBB3_1
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; RV32I-NEXT: .LBB3_1: # %cond.false
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; RV32I-NEXT: addi a0, a1, -1
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: andi a1, a0, 255
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; RV32I-NEXT: beqz a1, .LBB3_1
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; RV32I-NEXT: # %bb.2: # %cond.false
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; RV32I-NEXT: addi a1, a0, -1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: lui a1, 349525
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; RV32I-NEXT: addi a1, a1, 1365
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; RV32I-NEXT: srli a2, a0, 1
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@ -138,7 +135,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
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; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
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; RV32I-NEXT: jalr a2
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; RV32I-NEXT: srli a0, a0, 24
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; RV32I-NEXT: .LBB3_2: # %cond.end
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; RV32I-NEXT: j .LBB3_3
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; RV32I-NEXT: .LBB3_1:
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; RV32I-NEXT: addi a0, zero, 8
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; RV32I-NEXT: .LBB3_3: # %cond.end
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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@ -154,17 +154,14 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: addi a0, zero, 16
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; RV32I-NEXT: lui a2, 16
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a2, a1, a2
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; RV32I-NEXT: beqz a2, .LBB4_2
|
||||
; RV32I-NEXT: j .LBB4_1
|
||||
; RV32I-NEXT: .LBB4_1: # %cond.false
|
||||
; RV32I-NEXT: addi a0, a1, -1
|
||||
; RV32I-NEXT: not a1, a1
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: lui a1, 16
|
||||
; RV32I-NEXT: addi a1, a1, -1
|
||||
; RV32I-NEXT: and a1, a0, a1
|
||||
; RV32I-NEXT: beqz a1, .LBB4_1
|
||||
; RV32I-NEXT: # %bb.2: # %cond.false
|
||||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
@ -187,7 +184,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: .LBB4_2: # %cond.end
|
||||
; RV32I-NEXT: j .LBB4_3
|
||||
; RV32I-NEXT: .LBB4_1:
|
||||
; RV32I-NEXT: addi a0, zero, 16
|
||||
; RV32I-NEXT: .LBB4_3: # %cond.end
|
||||
; RV32I-NEXT: lw s0, 8(sp)
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
@ -203,14 +203,11 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
|
||||
; RV32I-NEXT: sw ra, 12(sp)
|
||||
; RV32I-NEXT: sw s0, 8(sp)
|
||||
; RV32I-NEXT: addi s0, sp, 16
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: addi a0, zero, 32
|
||||
; RV32I-NEXT: beqz a1, .LBB5_2
|
||||
; RV32I-NEXT: j .LBB5_1
|
||||
; RV32I-NEXT: .LBB5_1: # %cond.false
|
||||
; RV32I-NEXT: addi a0, a1, -1
|
||||
; RV32I-NEXT: not a1, a1
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: beqz a0, .LBB5_1
|
||||
; RV32I-NEXT: # %bb.2: # %cond.false
|
||||
; RV32I-NEXT: addi a1, a0, -1
|
||||
; RV32I-NEXT: not a0, a0
|
||||
; RV32I-NEXT: and a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi a1, a1, 1365
|
||||
; RV32I-NEXT: srli a2, a0, 1
|
||||
@ -233,7 +230,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: .LBB5_2: # %cond.end
|
||||
; RV32I-NEXT: j .LBB5_3
|
||||
; RV32I-NEXT: .LBB5_1:
|
||||
; RV32I-NEXT: addi a0, zero, 32
|
||||
; RV32I-NEXT: .LBB5_3: # %cond.end
|
||||
; RV32I-NEXT: lw s0, 8(sp)
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
@ -249,13 +249,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
|
||||
; RV32I-NEXT: sw ra, 12(sp)
|
||||
; RV32I-NEXT: sw s0, 8(sp)
|
||||
; RV32I-NEXT: addi s0, sp, 16
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: addi a0, zero, 32
|
||||
; RV32I-NEXT: beqz a1, .LBB6_2
|
||||
; RV32I-NEXT: j .LBB6_1
|
||||
; RV32I-NEXT: .LBB6_1: # %cond.false
|
||||
; RV32I-NEXT: srli a0, a1, 1
|
||||
; RV32I-NEXT: or a0, a1, a0
|
||||
; RV32I-NEXT: beqz a0, .LBB6_1
|
||||
; RV32I-NEXT: # %bb.2: # %cond.false
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: or a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 2
|
||||
; RV32I-NEXT: or a0, a0, a1
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
@ -287,7 +284,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
|
||||
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
|
||||
; RV32I-NEXT: jalr a2
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: .LBB6_2: # %cond.end
|
||||
; RV32I-NEXT: j .LBB6_3
|
||||
; RV32I-NEXT: .LBB6_1:
|
||||
; RV32I-NEXT: addi a0, zero, 32
|
||||
; RV32I-NEXT: .LBB6_3: # %cond.end
|
||||
; RV32I-NEXT: lw s0, 8(sp)
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
@ -309,58 +309,61 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
|
||||
; RV32I-NEXT: sw s5, 20(sp)
|
||||
; RV32I-NEXT: sw s6, 16(sp)
|
||||
; RV32I-NEXT: sw s7, 12(sp)
|
||||
; RV32I-NEXT: sw s8, 8(sp)
|
||||
; RV32I-NEXT: addi s0, sp, 48
|
||||
; RV32I-NEXT: mv s1, a1
|
||||
; RV32I-NEXT: mv s2, a0
|
||||
; RV32I-NEXT: addi a0, s2, -1
|
||||
; RV32I-NEXT: not a1, s2
|
||||
; RV32I-NEXT: mv s2, a1
|
||||
; RV32I-NEXT: mv s3, a0
|
||||
; RV32I-NEXT: addi a0, s3, -1
|
||||
; RV32I-NEXT: not a1, s3
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi s4, a1, 1365
|
||||
; RV32I-NEXT: addi s5, a1, 1365
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: and a1, a1, s4
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi s5, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s5
|
||||
; RV32I-NEXT: addi s6, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s5
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi s3, a1, 257
|
||||
; RV32I-NEXT: addi s4, a1, 257
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi s6, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi s7, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s7
|
||||
; RV32I-NEXT: mv a1, s3
|
||||
; RV32I-NEXT: jalr s6
|
||||
; RV32I-NEXT: addi a1, s1, -1
|
||||
; RV32I-NEXT: not a2, s1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: srli a2, a1, 1
|
||||
; RV32I-NEXT: and a2, a2, s4
|
||||
; RV32I-NEXT: sub a1, a1, a2
|
||||
; RV32I-NEXT: and a2, a1, s5
|
||||
; RV32I-NEXT: srli a1, a1, 2
|
||||
; RV32I-NEXT: addi s8, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
; RV32I-NEXT: addi a0, s2, -1
|
||||
; RV32I-NEXT: not a1, s2
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: add a1, a2, a1
|
||||
; RV32I-NEXT: srli a2, a1, 4
|
||||
; RV32I-NEXT: add a1, a1, a2
|
||||
; RV32I-NEXT: and a1, a1, s7
|
||||
; RV32I-NEXT: srli s1, a0, 24
|
||||
; RV32I-NEXT: mv a0, a1
|
||||
; RV32I-NEXT: mv a1, s3
|
||||
; RV32I-NEXT: jalr s6
|
||||
; RV32I-NEXT: bnez s2, .LBB7_2
|
||||
; RV32I-NEXT: # %bb.1:
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: bnez s3, .LBB7_1
|
||||
; RV32I-NEXT: # %bb.2:
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: addi s1, a0, 32
|
||||
; RV32I-NEXT: .LBB7_2:
|
||||
; RV32I-NEXT: mv a0, s1
|
||||
; RV32I-NEXT: addi a0, a0, 32
|
||||
; RV32I-NEXT: j .LBB7_3
|
||||
; RV32I-NEXT: .LBB7_1:
|
||||
; RV32I-NEXT: srli a0, s1, 24
|
||||
; RV32I-NEXT: .LBB7_3:
|
||||
; RV32I-NEXT: mv a1, zero
|
||||
; RV32I-NEXT: lw s8, 8(sp)
|
||||
; RV32I-NEXT: lw s7, 12(sp)
|
||||
; RV32I-NEXT: lw s6, 16(sp)
|
||||
; RV32I-NEXT: lw s5, 20(sp)
|
||||
@ -509,58 +512,61 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
|
||||
; RV32I-NEXT: sw s5, 20(sp)
|
||||
; RV32I-NEXT: sw s6, 16(sp)
|
||||
; RV32I-NEXT: sw s7, 12(sp)
|
||||
; RV32I-NEXT: sw s8, 8(sp)
|
||||
; RV32I-NEXT: addi s0, sp, 48
|
||||
; RV32I-NEXT: mv s1, a1
|
||||
; RV32I-NEXT: mv s2, a0
|
||||
; RV32I-NEXT: addi a0, s2, -1
|
||||
; RV32I-NEXT: not a1, s2
|
||||
; RV32I-NEXT: mv s2, a1
|
||||
; RV32I-NEXT: mv s3, a0
|
||||
; RV32I-NEXT: addi a0, s3, -1
|
||||
; RV32I-NEXT: not a1, s3
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: lui a1, 349525
|
||||
; RV32I-NEXT: addi s4, a1, 1365
|
||||
; RV32I-NEXT: addi s5, a1, 1365
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: and a1, a1, s4
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 209715
|
||||
; RV32I-NEXT: addi s5, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s5
|
||||
; RV32I-NEXT: addi s6, a1, 819
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s5
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: lui a1, 4112
|
||||
; RV32I-NEXT: addi s3, a1, 257
|
||||
; RV32I-NEXT: addi s4, a1, 257
|
||||
; RV32I-NEXT: lui a1, %hi(__mulsi3)
|
||||
; RV32I-NEXT: addi s6, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
|
||||
; RV32I-NEXT: lui a1, 61681
|
||||
; RV32I-NEXT: addi s7, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s7
|
||||
; RV32I-NEXT: mv a1, s3
|
||||
; RV32I-NEXT: jalr s6
|
||||
; RV32I-NEXT: addi a1, s1, -1
|
||||
; RV32I-NEXT: not a2, s1
|
||||
; RV32I-NEXT: and a1, a2, a1
|
||||
; RV32I-NEXT: srli a2, a1, 1
|
||||
; RV32I-NEXT: and a2, a2, s4
|
||||
; RV32I-NEXT: sub a1, a1, a2
|
||||
; RV32I-NEXT: and a2, a1, s5
|
||||
; RV32I-NEXT: srli a1, a1, 2
|
||||
; RV32I-NEXT: addi s8, a1, -241
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: mv s1, a0
|
||||
; RV32I-NEXT: addi a0, s2, -1
|
||||
; RV32I-NEXT: not a1, s2
|
||||
; RV32I-NEXT: and a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 1
|
||||
; RV32I-NEXT: and a1, a1, s5
|
||||
; RV32I-NEXT: add a1, a2, a1
|
||||
; RV32I-NEXT: srli a2, a1, 4
|
||||
; RV32I-NEXT: add a1, a1, a2
|
||||
; RV32I-NEXT: and a1, a1, s7
|
||||
; RV32I-NEXT: srli s1, a0, 24
|
||||
; RV32I-NEXT: mv a0, a1
|
||||
; RV32I-NEXT: mv a1, s3
|
||||
; RV32I-NEXT: jalr s6
|
||||
; RV32I-NEXT: bnez s2, .LBB11_2
|
||||
; RV32I-NEXT: # %bb.1:
|
||||
; RV32I-NEXT: sub a0, a0, a1
|
||||
; RV32I-NEXT: and a1, a0, s6
|
||||
; RV32I-NEXT: srli a0, a0, 2
|
||||
; RV32I-NEXT: and a0, a0, s6
|
||||
; RV32I-NEXT: add a0, a1, a0
|
||||
; RV32I-NEXT: srli a1, a0, 4
|
||||
; RV32I-NEXT: add a0, a0, a1
|
||||
; RV32I-NEXT: and a0, a0, s8
|
||||
; RV32I-NEXT: mv a1, s4
|
||||
; RV32I-NEXT: jalr s7
|
||||
; RV32I-NEXT: bnez s3, .LBB11_1
|
||||
; RV32I-NEXT: # %bb.2:
|
||||
; RV32I-NEXT: srli a0, a0, 24
|
||||
; RV32I-NEXT: addi s1, a0, 32
|
||||
; RV32I-NEXT: .LBB11_2:
|
||||
; RV32I-NEXT: mv a0, s1
|
||||
; RV32I-NEXT: addi a0, a0, 32
|
||||
; RV32I-NEXT: j .LBB11_3
|
||||
; RV32I-NEXT: .LBB11_1:
|
||||
; RV32I-NEXT: srli a0, s1, 24
|
||||
; RV32I-NEXT: .LBB11_3:
|
||||
; RV32I-NEXT: mv a1, zero
|
||||
; RV32I-NEXT: lw s8, 8(sp)
|
||||
; RV32I-NEXT: lw s7, 12(sp)
|
||||
; RV32I-NEXT: lw s6, 16(sp)
|
||||
; RV32I-NEXT: lw s5, 20(sp)
|
||||
|
||||
@ -10,42 +10,37 @@ define void @jt(i32 %in, i32* %out) {
|
||||
; RV32I-NEXT: sw s0, 8(sp)
|
||||
; RV32I-NEXT: addi s0, sp, 16
|
||||
; RV32I-NEXT: addi a2, zero, 2
|
||||
; RV32I-NEXT: blt a2, a0, .LBB0_3
|
||||
; RV32I-NEXT: j .LBB0_1
|
||||
; RV32I-NEXT: .LBB0_1: # %entry
|
||||
; RV32I-NEXT: blt a2, a0, .LBB0_4
|
||||
; RV32I-NEXT: # %bb.1: # %entry
|
||||
; RV32I-NEXT: addi a3, zero, 1
|
||||
; RV32I-NEXT: beq a0, a3, .LBB0_5
|
||||
; RV32I-NEXT: j .LBB0_2
|
||||
; RV32I-NEXT: .LBB0_2: # %entry
|
||||
; RV32I-NEXT: beq a0, a2, .LBB0_6
|
||||
; RV32I-NEXT: j .LBB0_9
|
||||
; RV32I-NEXT: .LBB0_6: # %bb2
|
||||
; RV32I-NEXT: beq a0, a3, .LBB0_8
|
||||
; RV32I-NEXT: # %bb.2: # %entry
|
||||
; RV32I-NEXT: bne a0, a2, .LBB0_10
|
||||
; RV32I-NEXT: # %bb.3: # %bb2
|
||||
; RV32I-NEXT: addi a0, zero, 3
|
||||
; RV32I-NEXT: sw a0, 0(a1)
|
||||
; RV32I-NEXT: j .LBB0_9
|
||||
; RV32I-NEXT: .LBB0_3: # %entry
|
||||
; RV32I-NEXT: addi a3, zero, 3
|
||||
; RV32I-NEXT: beq a0, a3, .LBB0_7
|
||||
; RV32I-NEXT: j .LBB0_4
|
||||
; RV32I-NEXT: j .LBB0_10
|
||||
; RV32I-NEXT: .LBB0_4: # %entry
|
||||
; RV32I-NEXT: addi a3, zero, 3
|
||||
; RV32I-NEXT: beq a0, a3, .LBB0_9
|
||||
; RV32I-NEXT: # %bb.5: # %entry
|
||||
; RV32I-NEXT: addi a2, zero, 4
|
||||
; RV32I-NEXT: beq a0, a2, .LBB0_8
|
||||
; RV32I-NEXT: j .LBB0_9
|
||||
; RV32I-NEXT: .LBB0_8: # %bb4
|
||||
; RV32I-NEXT: bne a0, a2, .LBB0_10
|
||||
; RV32I-NEXT: # %bb.6: # %bb4
|
||||
; RV32I-NEXT: addi a0, zero, 1
|
||||
; RV32I-NEXT: sw a0, 0(a1)
|
||||
; RV32I-NEXT: .LBB0_9: # %exit
|
||||
; RV32I-NEXT: j .LBB0_10
|
||||
; RV32I-NEXT: .LBB0_8: # %bb1
|
||||
; RV32I-NEXT: addi a0, zero, 4
|
||||
; RV32I-NEXT: sw a0, 0(a1)
|
||||
; RV32I-NEXT: j .LBB0_10
|
||||
; RV32I-NEXT: .LBB0_9: # %bb3
|
||||
; RV32I-NEXT: sw a2, 0(a1)
|
||||
; RV32I-NEXT: .LBB0_10: # %exit
|
||||
; RV32I-NEXT: lw s0, 8(sp)
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: .LBB0_5: # %bb1
|
||||
; RV32I-NEXT: addi a0, zero, 4
|
||||
; RV32I-NEXT: sw a0, 0(a1)
|
||||
; RV32I-NEXT: j .LBB0_9
|
||||
; RV32I-NEXT: .LBB0_7: # %bb3
|
||||
; RV32I-NEXT: sw a2, 0(a1)
|
||||
; RV32I-NEXT: j .LBB0_9
|
||||
entry:
|
||||
switch i32 %in, label %exit [
|
||||
i32 1, label %bb1
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
|
||||
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32I %s
|
||||
|
||||
define i32 @foo(i32 %a, i32 *%b) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user