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[ARM][MVE] Add DoubleWidthResult flag
Add a flag for those instructions which read from the top/bottom halves of their inputs and produce a vector of results with double width elements. Differential Revision: https://reviews.llvm.org/D76762
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@ -410,6 +410,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
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bit validForTailPredication = 0;
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bit retainsPreviousHalfElement = 0;
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bit horizontalReduction = 0;
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bit doubleWidthResult = 0;
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// If this is a pseudo instruction, mark it isCodeGenOnly.
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let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
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@ -425,6 +426,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
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let TSFlags{20} = validForTailPredication;
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let TSFlags{21} = retainsPreviousHalfElement;
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let TSFlags{22} = horizontalReduction;
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let TSFlags{23} = doubleWidthResult;
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let Constraints = cstr;
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let Itinerary = itin;
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@ -2513,6 +2513,7 @@ class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U, bit top,
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let Inst{11-6} = 0b111101;
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let Inst{4} = 0b0;
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let Inst{0} = 0b0;
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let doubleWidthResult = 1;
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}
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multiclass MVE_VMOVL_m<bit top, string chr, MVEVectorVTInfo OutVTI,
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@ -2580,6 +2581,8 @@ class MVE_VSHLL_imm<string iname, string suffix, bit U, bit th,
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// For the MVE_VSHLL_patterns multiclass to refer to
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Operand immediateType = immtype;
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let doubleWidthResult = 1;
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}
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// The immediate VSHLL instructions accept shift counts from 1 up to
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@ -2623,6 +2626,7 @@ class MVE_VSHLL_by_lane_width<string iname, string suffix, bits<2> size,
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let Inst{11-6} = 0b111000;
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let Inst{4} = 0b0;
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let Inst{0} = 0b1;
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let doubleWidthResult = 1;
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}
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multiclass MVE_VSHLL_lw<string iname, string suffix, bits<2> sz, bit U,
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@ -4357,6 +4361,7 @@ class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
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let Inst{7} = Qn{3};
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let Inst{0} = 0b0;
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let validForTailPredication = 1;
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let doubleWidthResult = 1;
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}
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multiclass MVE_VMULL_m<MVEVectorVTInfo VTI,
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@ -4731,6 +4736,7 @@ class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
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let Inst{7} = Qn{3};
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let Inst{0} = 0b1;
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let validForTailPredication = 1;
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let doubleWidthResult = 1;
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}
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multiclass MVE_VQDMULL_m<string iname, MVEVectorVTInfo VTI, bit size, bit T,
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@ -4937,6 +4943,7 @@ class MVE_VQDMULL_qr<string iname, string suffix, bit size,
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let Inst{8} = 0b1;
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let Inst{5} = 0b1;
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let validForTailPredication = 1;
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let doubleWidthResult = 1;
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}
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multiclass MVE_VQDMULL_qr_m<string iname, MVEVectorVTInfo VTI, bit size,
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@ -403,6 +403,10 @@ namespace ARMII {
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// Whether the instruction produces a scalar result from vector operands.
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HorizontalReduction = 1 << 22,
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// Whether this instruction produces a vector result that is larger than
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// its input, typically reading from the top/bottom halves of the input(s).
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DoubleWidthResult = 1 << 23,
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//===------------------------------------------------------------------===//
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// Code domain.
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DomainShift = 15,
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@ -10,6 +10,103 @@
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using namespace llvm;
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TEST(MachineInstructionDoubleWidthResult, IsCorrect) {
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using namespace ARM;
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auto DoubleWidthResult = [](unsigned Opcode) {
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switch (Opcode) {
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default:
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break;
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case MVE_VMULLBp16:
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case MVE_VMULLBp8:
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case MVE_VMULLBs16:
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case MVE_VMULLBs32:
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case MVE_VMULLBs8:
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case MVE_VMULLBu16:
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case MVE_VMULLBu32:
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case MVE_VMULLBu8:
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case MVE_VMULLTp16:
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case MVE_VMULLTp8:
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case MVE_VMULLTs16:
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case MVE_VMULLTs32:
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case MVE_VMULLTs8:
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case MVE_VMULLTu16:
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case MVE_VMULLTu32:
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case MVE_VMULLTu8:
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case MVE_VQDMULL_qr_s16bh:
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case MVE_VQDMULL_qr_s16th:
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case MVE_VQDMULL_qr_s32bh:
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case MVE_VQDMULL_qr_s32th:
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case MVE_VQDMULLs16bh:
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case MVE_VQDMULLs16th:
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case MVE_VQDMULLs32bh:
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case MVE_VQDMULLs32th:
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case MVE_VMOVLs16bh:
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case MVE_VMOVLs16th:
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case MVE_VMOVLs8bh:
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case MVE_VMOVLs8th:
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case MVE_VMOVLu16bh:
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case MVE_VMOVLu16th:
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case MVE_VMOVLu8bh:
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case MVE_VMOVLu8th:
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case MVE_VSHLL_imms16bh:
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case MVE_VSHLL_imms16th:
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case MVE_VSHLL_imms8bh:
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case MVE_VSHLL_imms8th:
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case MVE_VSHLL_immu16bh:
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case MVE_VSHLL_immu16th:
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case MVE_VSHLL_immu8bh:
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case MVE_VSHLL_immu8th:
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case MVE_VSHLL_lws16bh:
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case MVE_VSHLL_lws16th:
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case MVE_VSHLL_lws8bh:
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case MVE_VSHLL_lws8th:
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case MVE_VSHLL_lwu16bh:
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case MVE_VSHLL_lwu16th:
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case MVE_VSHLL_lwu8bh:
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case MVE_VSHLL_lwu8th:
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return true;
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}
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return false;
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};
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LLVMInitializeARMTargetInfo();
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LLVMInitializeARMTarget();
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LLVMInitializeARMTargetMC();
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auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget(TT, Error);
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if (!T) {
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dbgs() << Error;
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return;
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}
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TargetOptions Options;
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auto TM = std::unique_ptr<LLVMTargetMachine>(
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static_cast<LLVMTargetMachine*>(
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T->createTargetMachine(TT, "generic", "", Options, None, None,
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CodeGenOpt::Default)));
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ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()),
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*static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
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const ARMBaseInstrInfo *TII = ST.getInstrInfo();
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auto MII = TM->getMCInstrInfo();
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for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
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const MCInstrDesc &Desc = TII->get(i);
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uint64_t Flags = Desc.TSFlags;
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if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
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continue;
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bool Valid = (Flags & ARMII::DoubleWidthResult) != 0;
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ASSERT_EQ(DoubleWidthResult(i), Valid)
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<< MII->getName(i)
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<< ": mismatched expectation for tail-predicated safety\n";
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}
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}
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TEST(MachineInstructionHorizontalReduction, IsCorrect) {
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using namespace ARM;
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@ -159,7 +256,6 @@ TEST(MachineInstructionHorizontalReduction, IsCorrect) {
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uint64_t Flags = Desc.TSFlags;
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if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
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continue;
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bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
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ASSERT_EQ(HorizontalReduction(i), Valid)
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<< MII->getName(i)
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