RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,

Browse Source 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.

llvm-svn: 128220
This commit is contained in:
Johnny Chen 2011-03-24 17:04:22 +00:00
parent a50ee2e148
commit 154393018f
3 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2946,6 +2946,8 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// of optional arguments is implemented.
if (Opcode == ARM::CPS3p) {
// Let's reject impossible imod values by returning false.
// AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
// invalid combination, so we just check for imod=0b00 here.
if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
return false;
MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod

4
test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# invalid (imod, M, iflags) combination
0x93 0x1c 0x02 0xf1

4
test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# core registers out of range
0xa5 0xba 0x52 0xed