mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
[DAGCombiner] Add general constant vector support to (srl (shl x, c), c) -> (and x, cst2)
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector llvm-svn: 284717
This commit is contained in:
parent
3bcf4fc907
commit
155b30ecf7
@ -4920,14 +4920,14 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
|
||||
}
|
||||
|
||||
// fold (srl (shl x, c), c) -> (and x, cst2)
|
||||
if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
|
||||
unsigned BitSize = N0.getScalarValueSizeInBits();
|
||||
if (BitSize <= 64) {
|
||||
uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
|
||||
SDLoc DL(N);
|
||||
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
|
||||
DAG.getConstant(~0ULL >> ShAmt, DL, VT));
|
||||
}
|
||||
if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
|
||||
isConstantOrConstantVector(N1, /* NoOpaques */ true)) {
|
||||
SDLoc DL(N);
|
||||
APInt AllBits = APInt::getAllOnesValue(N0.getScalarValueSizeInBits());
|
||||
SDValue Mask =
|
||||
DAG.getNode(ISD::SRL, DL, VT, DAG.getConstant(AllBits, DL, VT), N1);
|
||||
AddToWorklist(Mask.getNode());
|
||||
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), Mask);
|
||||
}
|
||||
|
||||
// fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
|
||||
|
@ -374,24 +374,12 @@ define <4 x i32> @combine_vec_lshr_shl_mask0(<4 x i32> %x) {
|
||||
define <4 x i32> @combine_vec_lshr_shl_mask1(<4 x i32> %x) {
|
||||
; SSE-LABEL: combine_vec_lshr_shl_mask1:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE-NEXT: psrld $5, %xmm1
|
||||
; SSE-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSE-NEXT: psrld $3, %xmm2
|
||||
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
||||
; SSE-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE-NEXT: psrld $4, %xmm1
|
||||
; SSE-NEXT: psrld $2, %xmm0
|
||||
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
||||
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
|
||||
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_vec_lshr_shl_mask1:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [2,3,4,5]
|
||||
; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%1 = shl <4 x i32> %x, <i32 2, i32 3, i32 4, i32 5>
|
||||
%2 = lshr <4 x i32> %1, <i32 2, i32 3, i32 4, i32 5>
|
||||
|
Loading…
Reference in New Issue
Block a user