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[PowerPC] Split the blr definition into BLR and BLR8

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We really need a separate 64-bit version of this instruction so that it can be
marked as clobbering LR8 (instead of just LR). No change in functionality
(although the verifier might be slightly happier), however, it is required for
stackmap/patchpoint support. Thus, this will be covered by stackmap test cases
once those are added.

llvm-svn: 225804
This commit is contained in:
Hal Finkel 2015-01-13 17:47:54 +00:00
parent 512c8bea3a
commit 155e99f749
5 changed files with 13 additions and 6 deletions
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2
lib/Target/PowerPC/PPCFastISel.cpp
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@ -1658,7 +1658,7 @@ bool PPCFastISel::SelectRet(const Instruction *I) {
}
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::BLR));
TII.get(PPC::BLR8));
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
MIB.addReg(RetRegs[i], RegState::Implicit);

4
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -871,6 +871,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
DebugLoc dl;
assert((RetOpcode == PPC::BLR ||
RetOpcode == PPC::BLR8 ||
RetOpcode == PPC::TCRETURNri ||
RetOpcode == PPC::TCRETURNdi ||
RetOpcode == PPC::TCRETURNai ||
@ -1057,7 +1058,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
// Callee pop calling convention. Pop parameter/linkage area. Used for tail
// call optimization
if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
if (MF.getTarget().Options.GuaranteedTailCallOpt &&
(RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
MF.getFunction()->getCallingConv() == CallingConv::Fast) {
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
unsigned CallerAllocatedAmt = FI->getMinReservedArea();

3
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -81,6 +81,9 @@ def HI48_64 : SDNodeXForm<imm, [{
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isReturn = 1, Uses = [LR8, RM] in
def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(retflag)]>, Requires<[In64BitMode]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>,

8
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1113,7 +1113,7 @@ bool PPCInstrInfo::PredicateInstruction(
MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const {
unsigned OpC = MI->getOpcode();
if (OpC == PPC::BLR) {
if (OpC == PPC::BLR || OpC == PPC::BLR8) {
if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
bool isPPC64 = Subtarget.isPPC64();
MI->setDesc(get(Pred[0].getImm() ?
@ -1277,6 +1277,7 @@ bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
return false;
case PPC::B:
case PPC::BLR:
case PPC::BLR8:
case PPC::BCTR:
case PPC::BCTR8:
case PPC::BCTRL:
@ -2138,7 +2139,8 @@ protected:
I = ReturnMBB.SkipPHIsAndLabels(I);
// The block must be essentially empty except for the blr.
if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
if (I == ReturnMBB.end() ||
(I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
I != ReturnMBB.getLastNonDebugInstr())
return Changed;
@ -2151,7 +2153,7 @@ protected:
if (J->getOperand(0).getMBB() == &ReturnMBB) {
// This is an unconditional branch to the return. Replace the
// branch with a blr.
BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()));
MachineBasicBlock::iterator K = J--;
K->eraseFromParent();
BlockChanged = true;

2
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1016,7 +1016,7 @@ def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isReturn = 1, Uses = [LR, RM] in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
[(retflag)]>;
[(retflag)]>, Requires<[In32BitMode]>;
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>;