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[M68k] Refactor codegen patterns for logic operations and add tests for it
Refactor pat for and, or and xor operation and add missing tests for it Reviewed By: myhsu Differential Revision: https://reviews.llvm.org/D104626
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Jim Lin
parent
1073014a44
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155f1c4b36
@ -858,35 +858,23 @@ def : Pat<(sube i8 :$src, i8 :$opd), (SUBX8dd MxDRD8 :$src, MxDRD8 :$opd)>;
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def : Pat<(sube i16:$src, i16:$opd), (SUBX16dd MxDRD16:$src, MxDRD16:$opd)>;
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def : Pat<(sube i32:$src, i32:$opd), (SUBX32dd MxDRD32:$src, MxDRD32:$opd)>;
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multiclass BitwisePat<string INST, SDNode OP> {
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// op reg, reg
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def : Pat<(OP i8 :$src, i8 :$opd),
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(!cast<MxInst>(INST#"8dd") MxDRD8 :$src, MxDRD8 :$opd)>;
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def : Pat<(OP i16:$src, i16:$opd),
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(!cast<MxInst>(INST#"16dd") MxDRD16:$src, MxDRD16:$opd)>;
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def : Pat<(OP i32:$src, i32:$opd),
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(!cast<MxInst>(INST#"32dd") MxDRD32:$src, MxDRD32:$opd)>;
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// op reg, imm
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def : Pat<(OP i8: $src, MximmSExt8 :$opd),
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(!cast<MxInst>(INST#"8di") MxDRD8 :$src, imm:$opd)>;
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def : Pat<(OP i16:$src, MximmSExt16:$opd),
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(!cast<MxInst>(INST#"16di") MxDRD16:$src, imm:$opd)>;
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def : Pat<(OP i32:$src, MximmSExt32:$opd),
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(!cast<MxInst>(INST#"32di") MxDRD32:$src, imm:$opd)>;
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}
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// and reg, reg
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def : Pat<(and i8 :$src, i8 :$opd), (AND8dd MxDRD8 :$src, MxDRD8 :$opd)>;
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def : Pat<(and i16:$src, i16:$opd), (AND16dd MxDRD16:$src, MxDRD16:$opd)>;
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def : Pat<(and i32:$src, i32:$opd), (AND32dd MxDRD32:$src, MxDRD32:$opd)>;
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// and reg, imm
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def : Pat<(and i8: $src, MximmSExt8 :$opd), (AND8di MxDRD8 :$src, imm:$opd)>;
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def : Pat<(and i16:$src, MximmSExt16:$opd), (AND16di MxDRD16:$src, imm:$opd)>;
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def : Pat<(and i32:$src, MximmSExt32:$opd), (AND32di MxDRD32:$src, imm:$opd)>;
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// xor reg,reg
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def : Pat<(xor i8 :$src, i8 :$opd), (XOR8dd MxDRD8 :$src, MxDRD8 :$opd)>;
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def : Pat<(xor i16:$src, i16:$opd), (XOR16dd MxDRD16:$src, MxDRD16:$opd)>;
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def : Pat<(xor i32:$src, i32:$opd), (XOR32dd MxDRD32:$src, MxDRD32:$opd)>;
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// xor reg, imm
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def : Pat<(xor i8: $src, MximmSExt8 :$opd), (XOR8di MxDRD8 :$src, imm:$opd)>;
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def : Pat<(xor i16:$src, MximmSExt16:$opd), (XOR16di MxDRD16:$src, imm:$opd)>;
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def : Pat<(xor i32:$src, MximmSExt32:$opd), (XOR32di MxDRD32:$src, imm:$opd)>;
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// or reg, reg
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def : Pat<(or i8 :$src, i8 :$opd), (OR8dd MxDRD8 :$src, MxDRD8 :$opd)>;
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def : Pat<(or i16:$src, i16:$opd), (OR16dd MxDRD16:$src, MxDRD16:$opd)>;
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def : Pat<(or i32:$src, i32:$opd), (OR32dd MxDRD32:$src, MxDRD32:$opd)>;
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// or reg, imm
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def : Pat<(or i8: $src, MximmSExt8 :$opd), (OR8di MxDRD8 :$src, imm:$opd)>;
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def : Pat<(or i16:$src, MximmSExt16:$opd), (OR16di MxDRD16:$src, imm:$opd)>;
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def : Pat<(or i32:$src, MximmSExt32:$opd), (OR32di MxDRD32:$src, imm:$opd)>;
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defm : BitwisePat<"AND", and>;
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defm : BitwisePat<"OR", or>;
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defm : BitwisePat<"XOR", xor>;
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232
test/CodeGen/M68k/Arith/bitwise.ll
Normal file
232
test/CodeGen/M68k/Arith/bitwise.ll
Normal file
@ -0,0 +1,232 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
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; op reg, reg
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define zeroext i8 @andb(i8 zeroext %a, i8 zeroext %b) nounwind {
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; CHECK-LABEL: andb:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.b (11,%sp), %d0
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; CHECK-NEXT: move.b (7,%sp), %d1
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; CHECK-NEXT: and.b %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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%1 = and i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @andw(i16 zeroext %a, i16 zeroext %b) nounwind {
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; CHECK-LABEL: andw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: move.w (6,%sp), %d1
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; CHECK-NEXT: and.w %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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%1 = and i16 %a, %b
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ret i16 %1
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}
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define i32 @andl(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: andl:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (8,%sp), %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: and.l %d1, %d0
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; CHECK-NEXT: rts
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%1 = and i32 %a, %b
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ret i32 %1
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}
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define zeroext i8 @orb(i8 zeroext %a, i8 zeroext %b) nounwind {
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; CHECK-LABEL: orb:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.b (11,%sp), %d0
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; CHECK-NEXT: move.b (7,%sp), %d1
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; CHECK-NEXT: or.b %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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%1 = or i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @orw(i16 zeroext %a, i16 zeroext %b) nounwind {
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; CHECK-LABEL: orw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: move.w (6,%sp), %d1
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; CHECK-NEXT: or.w %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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%1 = or i16 %a, %b
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ret i16 %1
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}
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define i32 @orl(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: orl:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (8,%sp), %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: or.l %d1, %d0
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; CHECK-NEXT: rts
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%1 = or i32 %a, %b
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ret i32 %1
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}
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define zeroext i8 @eorb(i8 zeroext %a, i8 zeroext %b) nounwind {
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; CHECK-LABEL: eorb:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.b (11,%sp), %d0
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; CHECK-NEXT: move.b (7,%sp), %d1
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; CHECK-NEXT: eor.b %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #255, %d0
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; CHECK-NEXT: rts
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%1 = xor i8 %a, %b
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ret i8 %1
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}
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define zeroext i16 @eorw(i16 zeroext %a, i16 zeroext %b) nounwind {
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; CHECK-LABEL: eorw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.w (10,%sp), %d0
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; CHECK-NEXT: move.w (6,%sp), %d1
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; CHECK-NEXT: eor.w %d0, %d1
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; CHECK-NEXT: move.l %d1, %d0
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; CHECK-NEXT: and.l #65535, %d0
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; CHECK-NEXT: rts
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%1 = xor i16 %a, %b
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ret i16 %1
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}
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define i32 @eorl(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: eorl:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (8,%sp), %d1
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: eor.l %d1, %d0
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; CHECK-NEXT: rts
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%1 = xor i32 %a, %b
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ret i32 %1
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}
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; op reg, imm
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; For type i8 and i16, value is loaded from memory to avoid optimizing it to *.l
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define void @andib(i8* %a) nounwind {
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; CHECK-LABEL: andib:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.b (%a0), %d0
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; CHECK-NEXT: and.b #18, %d0
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; CHECK-NEXT: move.b %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i8, i8* %a
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%2 = and i8 %1, 18
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store i8 %2, i8* %a
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ret void
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}
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define void @andiw(i16* %a) nounwind {
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; CHECK-LABEL: andiw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.w (%a0), %d0
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; CHECK-NEXT: and.w #4660, %d0
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; CHECK-NEXT: move.w %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i16, i16* %a
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%2 = and i16 %1, 4660
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store i16 %2, i16* %a
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ret void
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}
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define i32 @andil(i32 %a) nounwind {
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; CHECK-LABEL: andil:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: and.l #305419896, %d0
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; CHECK-NEXT: rts
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%1 = and i32 %a, 305419896
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ret i32 %1
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}
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define void @orib(i8* %a) nounwind {
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; CHECK-LABEL: orib:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.b (%a0), %d0
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; CHECK-NEXT: or.b #18, %d0
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; CHECK-NEXT: move.b %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i8, i8* %a
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%2 = or i8 %1, 18
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store i8 %2, i8* %a
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ret void
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}
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define void @oriw(i16* %a) nounwind {
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; CHECK-LABEL: oriw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.w (%a0), %d0
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; CHECK-NEXT: or.w #4660, %d0
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; CHECK-NEXT: move.w %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i16, i16* %a
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%2 = or i16 %1, 4660
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store i16 %2, i16* %a
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ret void
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}
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define i32 @oril(i32 %a) nounwind {
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; CHECK-LABEL: oril:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: or.l #305419896, %d0
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; CHECK-NEXT: rts
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%1 = or i32 %a, 305419896
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ret i32 %1
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}
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define void @eorib(i8* %a) nounwind {
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; CHECK-LABEL: eorib:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.b (%a0), %d0
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; CHECK-NEXT: eori.b #18, %d0
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; CHECK-NEXT: move.b %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i8, i8* %a
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%2 = xor i8 %1, 18
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store i8 %2, i8* %a
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ret void
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}
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define void @eoriw(i16* %a) nounwind {
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; CHECK-LABEL: eoriw:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %a0
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; CHECK-NEXT: move.w (%a0), %d0
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; CHECK-NEXT: eori.w #4660, %d0
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; CHECK-NEXT: move.w %d0, (%a0)
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; CHECK-NEXT: rts
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%1 = load i16, i16* %a
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%2 = xor i16 %1, 4660
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store i16 %2, i16* %a
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ret void
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}
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define i32 @eoril(i32 %a) nounwind {
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; CHECK-LABEL: eoril:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: move.l (4,%sp), %d0
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; CHECK-NEXT: eori.l #305419896, %d0
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; CHECK-NEXT: rts
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%1 = xor i32 %a, 305419896
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ret i32 %1
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}
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