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[AArch64] Regenerate some tests checks. NFC

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This commit is contained in:
David Green 2021-07-20 14:52:36 +01:00
parent 9e495cac81
commit 1560f33a55
3 changed files with 197 additions and 74 deletions
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123
test/CodeGen/AArch64/bf16-vector-bitcast.ll
View File

@ -1,9 +1,11 @@
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v4i16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <4 x i16>
ret <4 x i16> %1
@ -11,8 +13,9 @@ entry:
define <2 x i32> @v4bf16_to_v2i32(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v2i32:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <2 x i32>
ret <2 x i32> %1
@ -20,8 +23,9 @@ entry:
define <1 x i64> @v4bf16_to_v1i64(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v1i64:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <1 x i64>
ret <1 x i64> %1
@ -29,8 +33,9 @@ entry:
define i64 @v4bf16_to_i64(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_i64:
; CHECK-NEXT: fmov x0, d1
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov x0, d1
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to i64
ret i64 %1
@ -38,8 +43,9 @@ entry:
define <2 x float> @v4bf16_to_v2float(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v2float:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <2 x float>
ret <2 x float> %1
@ -47,8 +53,9 @@ entry:
define <1 x double> @v4bf16_to_v1double(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_v1double:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to <1 x double>
ret <1 x double> %1
@ -56,8 +63,9 @@ entry:
define double @v4bf16_to_double(float, <4 x bfloat> %a) nounwind {
; CHECK-LABEL: v4bf16_to_double:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x bfloat> %a to double
ret double %1
@ -66,8 +74,9 @@ entry:
define <4 x bfloat> @v4i16_to_v4bf16(float, <4 x i16> %a) nounwind {
; CHECK-LABEL: v4i16_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x i16> %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -75,8 +84,9 @@ entry:
define <4 x bfloat> @v2i32_to_v4bf16(float, <2 x i32> %a) nounwind {
; CHECK-LABEL: v2i32_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x i32> %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -84,8 +94,9 @@ entry:
define <4 x bfloat> @v1i64_to_v4bf16(float, <1 x i64> %a) nounwind {
; CHECK-LABEL: v1i64_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <1 x i64> %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -93,8 +104,9 @@ entry:
define <4 x bfloat> @i64_to_v4bf16(float, i64 %a) nounwind {
; CHECK-LABEL: i64_to_v4bf16:
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: ret
entry:
%1 = bitcast i64 %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -102,8 +114,9 @@ entry:
define <4 x bfloat> @v2float_to_v4bf16(float, <2 x float> %a) nounwind {
; CHECK-LABEL: v2float_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x float> %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -111,8 +124,9 @@ entry:
define <4 x bfloat> @v1double_to_v4bf16(float, <1 x double> %a) nounwind {
; CHECK-LABEL: v1double_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <1 x double> %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -120,8 +134,9 @@ entry:
define <4 x bfloat> @double_to_v4bf16(float, double %a) nounwind {
; CHECK-LABEL: double_to_v4bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast double %a to <4 x bfloat>
ret <4 x bfloat> %1
@ -129,8 +144,9 @@ entry:
define <8 x i16> @v8bf16_to_v8i16(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v8i16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <8 x i16>
ret <8 x i16> %1
@ -138,8 +154,9 @@ entry:
define <4 x i32> @v8bf16_to_v4i32(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v4i32:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <4 x i32>
ret <4 x i32> %1
@ -147,8 +164,9 @@ entry:
define <2 x i64> @v8bf16_to_v2i64(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v2i64:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <2 x i64>
ret <2 x i64> %1
@ -156,8 +174,9 @@ entry:
define <4 x float> @v8bf16_to_v4float(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v4float:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <4 x float>
ret <4 x float> %1
@ -165,8 +184,9 @@ entry:
define <2 x double> @v8bf16_to_v2double(float, <8 x bfloat> %a) nounwind {
; CHECK-LABEL: v8bf16_to_v2double:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x bfloat> %a to <2 x double>
ret <2 x double> %1
@ -174,8 +194,9 @@ entry:
define <8 x bfloat> @v8i16_to_v8bf16(float, <8 x i16> %a) nounwind {
; CHECK-LABEL: v8i16_to_v8bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x i16> %a to <8 x bfloat>
ret <8 x bfloat> %1
@ -183,8 +204,9 @@ entry:
define <8 x bfloat> @v4i32_to_v8bf16(float, <4 x i32> %a) nounwind {
; CHECK-LABEL: v4i32_to_v8bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x i32> %a to <8 x bfloat>
ret <8 x bfloat> %1
@ -192,8 +214,9 @@ entry:
define <8 x bfloat> @v2i64_to_v8bf16(float, <2 x i64> %a) nounwind {
; CHECK-LABEL: v2i64_to_v8bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x i64> %a to <8 x bfloat>
ret <8 x bfloat> %1
@ -201,8 +224,9 @@ entry:
define <8 x bfloat> @v4float_to_v8bf16(float, <4 x float> %a) nounwind {
; CHECK-LABEL: v4float_to_v8bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x float> %a to <8 x bfloat>
ret <8 x bfloat> %1
@ -210,8 +234,9 @@ entry:
define <8 x bfloat> @v2double_to_v8bf16(float, <2 x double> %a) nounwind {
; CHECK-LABEL: v2double_to_v8bf16:
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x double> %a to <8 x bfloat>
ret <8 x bfloat> %1

51
test/CodeGen/AArch64/bf16-vector-shuffle.ll
View File

@ -1,9 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
; bfloat16x4_t test_vcreate_bf16(uint64_t a) { return vcreate_bf16(a); }
define <4 x bfloat> @test_vcreate_bf16(i64 %a) nounwind {
; CHECK-LABEL: test_vcreate_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: ret
entry:
@ -14,6 +15,8 @@ entry:
; bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) { return vdup_n_bf16(v); }
define <4 x bfloat> @test_vdup_n_bf16(bfloat %v) nounwind {
; CHECK-LABEL: test_vdup_n_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-NEXT: dup v0.4h, v0.h[0]
; CHECK-NEXT: ret
entry:
@ -25,6 +28,8 @@ entry:
; bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) { return vdupq_n_bf16(v); }
define <8 x bfloat> @test_vdupq_n_bf16(bfloat %v) nounwind {
; CHECK-LABEL: test_vdupq_n_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-NEXT: dup v0.8h, v0.h[0]
; CHECK-NEXT: ret
entry:
@ -36,6 +41,8 @@ entry:
; bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) { return vdup_lane_bf16(v, 1); }
define <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vdup_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.4h, v0.h[1]
; CHECK-NEXT: ret
entry:
@ -46,6 +53,8 @@ entry:
; bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) { return vdupq_lane_bf16(v, 1); }
define <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vdupq_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.8h, v0.h[1]
; CHECK-NEXT: ret
entry:
@ -56,6 +65,7 @@ entry:
; bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) { return vdup_laneq_bf16(v, 7); }
define <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vdup_laneq_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: dup v0.4h, v0.h[7]
; CHECK-NEXT: ret
entry:
@ -66,6 +76,7 @@ entry:
; bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) { return vdupq_laneq_bf16(v, 7); }
define <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vdupq_laneq_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: dup v0.8h, v0.h[7]
; CHECK-NEXT: ret
entry:
@ -76,6 +87,9 @@ entry:
; bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) { return vcombine_bf16(low, high); }
define <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> %low, <4 x bfloat> %high) nounwind {
; CHECK-LABEL: test_vcombine_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: ret
entry:
@ -86,7 +100,9 @@ entry:
; bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) { return vget_high_bf16(a); }
define <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) nounwind {
; CHECK-LABEL: test_vget_high_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@ -96,6 +112,8 @@ entry:
; bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) { return vget_low_bf16(a); }
define <4 x bfloat> @test_vget_low_bf16(<8 x bfloat> %a) nounwind {
; CHECK-LABEL: test_vget_low_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@ -105,6 +123,8 @@ entry:
; bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) { return vget_lane_bf16(v, 1); }
define bfloat @test_vget_lane_bf16(<4 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vget_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: ret
entry:
@ -115,6 +135,7 @@ entry:
; bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) { return vgetq_lane_bf16(v, 7); }
define bfloat @test_vgetq_lane_bf16(<8 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vgetq_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov h0, v0.h[7]
; CHECK-NEXT: ret
entry:
@ -125,6 +146,9 @@ entry:
; bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) { return vset_lane_bf16(a, v, 1); }
define <4 x bfloat> @test_vset_lane_bf16(bfloat %a, <4 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vset_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-NEXT: mov v1.h[1], v0.h[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
@ -136,6 +160,8 @@ entry:
; bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) { return vsetq_lane_bf16(a, v, 7); }
define <8 x bfloat> @test_vsetq_lane_bf16(bfloat %a, <8 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vsetq_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-NEXT: mov v1.h[7], v0.h[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
@ -147,6 +173,8 @@ entry:
; bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) { return vduph_lane_bf16(v, 1); }
define bfloat @test_vduph_lane_bf16(<4 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vduph_lane_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h0, v0.h[1]
; CHECK-NEXT: ret
entry:
@ -157,6 +185,7 @@ entry:
; bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) { return vduph_laneq_bf16(v, 7); }
define bfloat @test_vduph_laneq_bf16(<8 x bfloat> %v) nounwind {
; CHECK-LABEL: test_vduph_laneq_bf16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov h0, v0.h[7]
; CHECK-NEXT: ret
entry:
@ -167,7 +196,11 @@ entry:
; vcopy_lane_bf16(a, 1, b, 3);
define <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> %a, <4 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopy_lane_bf16_v1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.h[1], v1.h[3]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%vset_lane = shufflevector <4 x bfloat> %a, <4 x bfloat> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
@ -177,7 +210,11 @@ entry:
; vcopy_lane_bf16(a, 2, b, 0);
define <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> %a, <4 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopy_lane_bf16_v2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.h[2], v1.h[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%vset_lane = shufflevector <4 x bfloat> %a, <4 x bfloat> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
@ -187,6 +224,8 @@ entry:
; vcopyq_lane_bf16(a, 0, b, 2);
define <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> %a, <4 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopyq_lane_bf16_v1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.h[0], v1.h[2]
; CHECK-NEXT: ret
entry:
@ -198,6 +237,8 @@ entry:
; vcopyq_lane_bf16(a, 6, b, 0);
define <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> %a, <4 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopyq_lane_bf16_v2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.h[6], v1.h[0]
; CHECK-NEXT: ret
entry:
@ -209,7 +250,10 @@ entry:
; vcopy_laneq_bf16(a, 0, b, 7);
define <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> %a, <8 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopy_laneq_bf16_v1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov v0.h[0], v1.h[7]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%vgetq_lane = extractelement <8 x bfloat> %b, i32 7
@ -220,7 +264,10 @@ entry:
; vcopy_laneq_bf16(a, 3, b, 4);
define <4 x bfloat> @test_vcopy_laneq_bf16_v2(<4 x bfloat> %a, <8 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopy_laneq_bf16_v2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov v0.h[3], v1.h[4]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
entry:
%vgetq_lane = extractelement <8 x bfloat> %b, i32 4
@ -231,6 +278,7 @@ entry:
; vcopyq_laneq_bf16(a, 3, b, 7);
define <8 x bfloat> @test_vcopyq_laneq_bf16_v1(<8 x bfloat> %a, <8 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopyq_laneq_bf16_v1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.h[3], v1.h[7]
; CHECK-NEXT: ret
entry:
@ -241,6 +289,7 @@ entry:
; vcopyq_laneq_bf16(a, 6, b, 2);
define <8 x bfloat> @test_vcopyq_laneq_bf16_v2(<8 x bfloat> %a, <8 x bfloat> %b) nounwind {
; CHECK-LABEL: test_vcopyq_laneq_bf16_v2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.h[6], v1.h[2]
; CHECK-NEXT: ret
entry:

97
test/CodeGen/AArch64/fp16-vector-bitcast.ll
View File

@ -1,8 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v4i16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <4 x i16>
ret <4 x i16> %1
@ -10,7 +13,9 @@ entry:
define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v2i32:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <2 x i32>
ret <2 x i32> %1
@ -18,7 +23,9 @@ entry:
define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v1i64:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <1 x i64>
ret <1 x i64> %1
@ -26,7 +33,9 @@ entry:
define i64 @v4f16_to_i64(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_i64:
; CHECK: fmov x0, d1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov x0, d1
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to i64
ret i64 %1
@ -34,7 +43,9 @@ entry:
define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v2float:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <2 x float>
ret <2 x float> %1
@ -42,7 +53,9 @@ entry:
define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_v1double:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to <1 x double>
ret <1 x double> %1
@ -50,7 +63,9 @@ entry:
define double @v4f16_to_double(float, <4 x half> %a) #0 {
; CHECK-LABEL: v4f16_to_double:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x half> %a to double
ret double %1
@ -59,7 +74,9 @@ entry:
define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 {
; CHECK-LABEL: v4i16_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x i16> %a to <4 x half>
ret <4 x half> %1
@ -67,7 +84,9 @@ entry:
define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 {
; CHECK-LABEL: v2i32_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x i32> %a to <4 x half>
ret <4 x half> %1
@ -75,7 +94,9 @@ entry:
define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 {
; CHECK-LABEL: v1i64_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <1 x i64> %a to <4 x half>
ret <4 x half> %1
@ -83,7 +104,9 @@ entry:
define <4 x half> @i64_to_v4f16(float, i64 %a) #0 {
; CHECK-LABEL: i64_to_v4f16:
; CHECK: fmov d0, x0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: ret
entry:
%1 = bitcast i64 %a to <4 x half>
ret <4 x half> %1
@ -91,7 +114,9 @@ entry:
define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 {
; CHECK-LABEL: v2float_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x float> %a to <4 x half>
ret <4 x half> %1
@ -99,7 +124,9 @@ entry:
define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 {
; CHECK-LABEL: v1double_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <1 x double> %a to <4 x half>
ret <4 x half> %1
@ -107,7 +134,9 @@ entry:
define <4 x half> @double_to_v4f16(float, double %a) #0 {
; CHECK-LABEL: double_to_v4f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast double %a to <4 x half>
ret <4 x half> %1
@ -124,7 +153,9 @@ entry:
define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 {
; CHECK-LABEL: v8f16_to_v8i16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <8 x i16>
ret <8 x i16> %1
@ -132,7 +163,9 @@ entry:
define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 {
; CHECK-LABEL: v8f16_to_v4i32:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <4 x i32>
ret <4 x i32> %1
@ -140,7 +173,9 @@ entry:
define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 {
; CHECK-LABEL: v8f16_to_v2i64:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <2 x i64>
ret <2 x i64> %1
@ -148,7 +183,9 @@ entry:
define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 {
; CHECK-LABEL: v8f16_to_v4float:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <4 x float>
ret <4 x float> %1
@ -156,7 +193,9 @@ entry:
define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 {
; CHECK-LABEL: v8f16_to_v2double:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x half> %a to <2 x double>
ret <2 x double> %1
@ -164,7 +203,9 @@ entry:
define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 {
; CHECK-LABEL: v8i16_to_v8f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <8 x i16> %a to <8 x half>
ret <8 x half> %1
@ -172,7 +213,9 @@ entry:
define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 {
; CHECK-LABEL: v4i32_to_v8f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x i32> %a to <8 x half>
ret <8 x half> %1
@ -180,7 +223,9 @@ entry:
define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 {
; CHECK-LABEL: v2i64_to_v8f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x i64> %a to <8 x half>
ret <8 x half> %1
@ -188,7 +233,9 @@ entry:
define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 {
; CHECK-LABEL: v4float_to_v8f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <4 x float> %a to <8 x half>
ret <8 x half> %1
@ -196,7 +243,9 @@ entry:
define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 {
; CHECK-LABEL: v2double_to_v8f16:
; CHECK: mov v0.16b, v1.16b
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret
entry:
%1 = bitcast <2 x double> %a to <8 x half>
ret <8 x half> %1