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[GlobalISel][AArch64] Select G_FEXP

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This teaches the legalizer to handle G_FEXP in AArch64. As a result, it also
allows us to select G_FEXP.

It...

- Updates the legalizer-info tests
- Adds a test for legalizing exp
- Updates the existing fp tests to show that we can now select G_FEXP

https://reviews.llvm.org/D57483

llvm-svn: 352692
This commit is contained in:
Jessica Paquette 2019-01-30 23:46:15 +00:00
parent 4ff1612c12
commit 156cec86e5
7 changed files with 269 additions and 3 deletions
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7
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -115,6 +115,9 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
case TargetOpcode::G_FDIV:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
case TargetOpcode::G_FEXP:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
case TargetOpcode::G_FREM:
return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
case TargetOpcode::G_FPOW:
@ -238,7 +241,8 @@ LegalizerHelper::libcall(MachineInstr &MI) {
case TargetOpcode::G_FSIN:
case TargetOpcode::G_FLOG10:
case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2: {
case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FEXP: {
if (Size > 64) {
LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
return UnableToLegalize;
@ -1206,6 +1210,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FEXP:
assert(TypeIdx == 0);
Observer.changingInstr(MI);

3
lib/Target/AArch64/AArch64LegalizerInfo.cpp
View File

@ -143,7 +143,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
[=](const LegalityQuery &Query) { return std::make_pair(0, s32); })
.legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16});
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2})
getActionDefinitionsBuilder(
{G_FCOS, G_FSIN, G_FLOG10, G_FLOG, G_FLOG2, G_FEXP})
// We need a call for these, so we always need to scalarize.
.scalarize(0)
// Regardless of FP16 support, widen 16-bit elements to 32-bits.

1
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -400,6 +400,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FSQRT:
case TargetOpcode::G_FABS:
case TargetOpcode::G_FEXP:
return true;
}
return false;

227
test/CodeGen/AArch64/GlobalISel/legalize-exp.mir Normal file
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@ -0,0 +1,227 @@
# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
# RUN: | FileCheck %s
...
---
name: test_v4f16.exp
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v4f16.exp
; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &expf
; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &expf
; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &expf
; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &expf
; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = G_FEXP %0
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.exp
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8f16.exp
; This is big, so let's just check for the 8 calls to expf, the the
; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought
; to be covered by the other tests.
; CHECK: G_UNMERGE_VALUES
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK: BL &expf
; CHECK-DAG: G_BUILD_VECTOR
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = G_FEXP %0
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f32.exp
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_v2f32.exp
; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V1]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V2]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: %1:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32)
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = G_FEXP %0
$d0 = COPY %1(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.exp
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v4f32.exp
; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V1]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V2]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V3]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: ADJCALLSTACKDOWN
; CHECK-DAG: $s0 = COPY [[V4]](s32)
; CHECK-DAG: BL &expf
; CHECK-DAG: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: %1:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32)
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_FEXP %0
$q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.exp
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v2f64.exp
; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-DAG: $d0 = COPY [[V1]](s64)
; CHECK-DAG: BL &exp
; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: ADJCALLSTACKDOWN
; CHECK-DAG: $d0 = COPY [[V2]](s64)
; CHECK-DAG: BL &exp
; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-DAG: ADJCALLSTACKUP
; CHECK-DAG: %1:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64)
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = G_FEXP %0
$q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: test_exp_half
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: test_exp_half
; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &expf
; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
%1:_(s16) = G_FEXP %0
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0

2
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
View File

@ -256,7 +256,7 @@
# DEBUG: .. the first uncovered type index: 1, OK
#
# DEBUG-NEXT: G_FEXP (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
# DEBUG: .. the first uncovered type index: 1, OK
#
# DEBUG-NEXT: G_FEXP2 (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined

20
test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
View File

@ -65,10 +65,14 @@ define %v4f16 @test_v4f16.pow(%v4f16 %a, %v4f16 %b) {
%1 = call %v4f16 @llvm.pow.v4f16(%v4f16 %a, %v4f16 %b)
ret %v4f16 %1
}
; FALLBACK-NOT: remark{{.*}}test_v4f16.exp
define %v4f16 @test_v4f16.exp(%v4f16 %a) {
; This operation is expanded, whether with or without +fullfp16.
; CHECK-LABEL: test_v4f16.exp:
; CHECK-COUNT-4: bl exp
; GISEL-LABEL: test_v4f16.exp:
; GISEL-COUNT-4: bl exp
%1 = call %v4f16 @llvm.exp.v4f16(%v4f16 %a)
ret %v4f16 %1
}
@ -262,10 +266,14 @@ define %v8f16 @test_v8f16.pow(%v8f16 %a, %v8f16 %b) {
%1 = call %v8f16 @llvm.pow.v8f16(%v8f16 %a, %v8f16 %b)
ret %v8f16 %1
}
; FALLBACK-NOT: remark{{.*}}test_v8f16.exp
define %v8f16 @test_v8f16.exp(%v8f16 %a) {
; This operation is expanded, whether with or without +fullfp16.
; CHECK-LABEL: test_v8f16.exp:
; CHECK-COUNT-8: bl exp
; GISEL-LABEL: test_v8f16.exp:
; GISEL-COUNT-8: bl exp
%1 = call %v8f16 @llvm.exp.v8f16(%v8f16 %a)
ret %v8f16 %1
}
@ -447,9 +455,13 @@ define %v2f32 @test_v2f32.pow(%v2f32 %a, %v2f32 %b) {
%1 = call %v2f32 @llvm.pow.v2f32(%v2f32 %a, %v2f32 %b)
ret %v2f32 %1
}
; FALLBACK-NOT: remark{{.*}}test_v2f32.exp
; CHECK: test_v2f32.exp:
; GISEL: test_v2f32.exp:
define %v2f32 @test_v2f32.exp(%v2f32 %a) {
; CHECK: exp
; GISEL: exp
%1 = call %v2f32 @llvm.exp.v2f32(%v2f32 %a)
ret %v2f32 %1
}
@ -599,9 +611,13 @@ define %v4f32 @test_v4f32.pow(%v4f32 %a, %v4f32 %b) {
%1 = call %v4f32 @llvm.pow.v4f32(%v4f32 %a, %v4f32 %b)
ret %v4f32 %1
}
; FALLBACK-NOT: remark{{.*}}test_v4f32.exp
; CHECK: test_v4f32.exp:
; GISEL: test_v4f32.exp:
define %v4f32 @test_v4f32.exp(%v4f32 %a) {
; CHECK: exp
; GISEL: exp
%1 = call %v4f32 @llvm.exp.v4f32(%v4f32 %a)
ret %v4f32 %1
}
@ -749,9 +765,13 @@ define %v2f64 @test_v2f64.pow(%v2f64 %a, %v2f64 %b) {
%1 = call %v2f64 @llvm.pow.v2f64(%v2f64 %a, %v2f64 %b)
ret %v2f64 %1
}
; FALLBACK-NOT: remark{{.*}}test_v2f64.exp
; CHECK: test_v2f64.exp:
; GISEL: test_v2f64.exp:
define %v2f64 @test_v2f64.exp(%v2f64 %a) {
; CHECK: exp
; GISEL: exp
%1 = call %v2f64 @llvm.exp.v2f64(%v2f64 %a)
ret %v2f64 %1
}

12
test/CodeGen/AArch64/f16-instructions.ll
View File

@ -886,6 +886,9 @@ define half @test_pow(half %a, half %b) #0 {
ret half %r
}
; FALLBACK-NOT: remark:{{.*}}test_exp
; FALLBACK-FP16-NOT: remark:{{.*}}test_exp
; CHECK-COMMON-LABEL: test_exp:
; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
; CHECK-COMMON-NEXT: mov x29, sp
@ -894,6 +897,15 @@ define half @test_pow(half %a, half %b) #0 {
; CHECK-COMMON-NEXT: fcvt h0, s0
; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
; CHECK-COMMON-NEXT: ret
; GISEL-LABEL: test_exp:
; GISEL-NEXT: stp x29, x30, [sp, #-16]!
; GISEL-NEXT: mov x29, sp
; GISEL-NEXT: fcvt s0, h0
; GISEL-NEXT: bl {{_?}}expf
; GISEL-NEXT: fcvt h0, s0
; GISEL-NEXT: ldp x29, x30, [sp], #16
; GISEL-NEXT: ret
define half @test_exp(half %a) #0 {
%r = call half @llvm.exp.f16(half %a)
ret half %r