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[PartialInliner]: Handle code regions in a switch stmt cases
This patch enhances computeOutliningColdRegionsInfo() to allow it to consider regions containing a single basic block and a single predecessor as candidate for partial inlining. Reviewed By: fhann Differential Revision: https://reviews.llvm.org/D89911
This commit is contained in:
Ettore Tiotto
parent
3fae7c2ab5
commit
157bbdf8a4
@ -414,11 +414,6 @@ PartialInlinerImpl::computeOutliningColdRegionsInfo(
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std::unique_ptr<FunctionOutliningMultiRegionInfo> OutliningInfo =
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std::make_unique<FunctionOutliningMultiRegionInfo>();
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auto IsSingleEntry = [](SmallVectorImpl<BasicBlock *> &BlockList) {
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BasicBlock *Dom = BlockList.front();
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return BlockList.size() > 1 && Dom->hasNPredecessors(1);
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};
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auto IsSingleExit =
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[&ORE](SmallVectorImpl<BasicBlock *> &BlockList) -> BasicBlock * {
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BasicBlock *ExitBlock = nullptr;
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@ -502,15 +497,24 @@ PartialInlinerImpl::computeOutliningColdRegionsInfo(
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SmallVector<BasicBlock *, 8> DominateVector;
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DT.getDescendants(*SI, DominateVector);
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assert(!DominateVector.empty() &&
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"SI should be reachable and have at least itself as descendant");
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// We can only outline single entry regions (for now).
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if (!IsSingleEntry(DominateVector))
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if (!DominateVector.front()->hasNPredecessors(1)) {
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LLVM_DEBUG(dbgs() << "ABORT: Block " << SI->getName()
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<< " doesn't have a single predecessor in the "
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"dominator tree\n";);
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continue;
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}
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BasicBlock *ExitBlock = nullptr;
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// We can only outline single exit regions (for now).
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if (!(ExitBlock = IsSingleExit(DominateVector)))
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if (!(ExitBlock = IsSingleExit(DominateVector))) {
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LLVM_DEBUG(dbgs() << "ABORT: Block " << SI->getName()
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<< " doesn't have a unique successor\n";);
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continue;
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}
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int OutlineRegionCost = 0;
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for (auto *BB : DominateVector)
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@ -519,7 +523,7 @@ PartialInlinerImpl::computeOutliningColdRegionsInfo(
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LLVM_DEBUG(dbgs() << "OutlineRegionCost = " << OutlineRegionCost
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<< "\n";);
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if (OutlineRegionCost < MinOutlineRegionCost) {
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if (!SkipCostAnalysis && OutlineRegionCost < MinOutlineRegionCost) {
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ORE.emit([&]() {
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return OptimizationRemarkAnalysis(DEBUG_TYPE, "TooCostly",
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&SI->front())
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@ -527,8 +531,12 @@ PartialInlinerImpl::computeOutliningColdRegionsInfo(
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<< " inline cost-savings smaller than "
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<< ore::NV("Cost", MinOutlineRegionCost);
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});
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LLVM_DEBUG(dbgs() << "ABORT: Outline region cost is smaller than "
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<< MinOutlineRegionCost << "\n";);
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continue;
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}
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// For now, ignore blocks that belong to a SISE region that is a
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// candidate for outlining. In the future, we may want to look
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// at inner regions because the outer region may have live-exit
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128
test/Transforms/PartialInlining/switch_stmt.ll
Normal file
128
test/Transforms/PartialInlining/switch_stmt.ll
Normal file
@ -0,0 +1,128 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes="partial-inliner" -skip-partial-inlining-cost-analysis -S < %s | FileCheck %s
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; RUN: opt -partial-inliner -skip-partial-inlining-cost-analysis -S < %s | FileCheck %s
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define dso_local signext i32 @callee(i32 signext %c1, i32 signext %c2) !prof !30 {
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; CHECK-LABEL: @callee(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: store i32 0, i32* [[RC]], align 4
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; CHECK-NEXT: switch i32 [[C1:%.*]], label [[SW_DEFAULT:%.*]] [
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; CHECK-NEXT: i32 0, label [[SW_BB:%.*]]
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; CHECK-NEXT: i32 1, label [[SW_BB1:%.*]]
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; CHECK-NEXT: i32 2, label [[SW_BB2:%.*]]
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; CHECK-NEXT: ], !prof !31
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; CHECK: sw.bb:
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; CHECK-NEXT: store i32 1, i32* [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG:%.*]]
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; CHECK: sw.bb1:
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; CHECK-NEXT: store i32 2, i32* [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.bb2:
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; CHECK-NEXT: store i32 4, i32* [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.default:
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; CHECK-NEXT: store i32 [[C2:%.*]], i32* [[RC]], align 4
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.epilog:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[RC]], align 4
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%rc = alloca i32, align 4
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store i32 0, i32* %rc, align 4
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switch i32 %c1, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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], !prof !31
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sw.bb: ;; cold
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store i32 1, i32* %rc, align 4
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br label %sw.epilog
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sw.bb1:
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store i32 2, i32* %rc, align 4
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br label %sw.epilog
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sw.bb2: ;; cold
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store i32 4, i32* %rc, align 4
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br label %sw.epilog
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sw.default:
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store i32 %c2, i32* %rc, align 4
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br label %sw.epilog
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sw.epilog:
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%0 = load i32, i32* %rc, align 4
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ret i32 %0
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}
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define dso_local signext i32 @caller(i32 signext %c) !prof !30 {
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; CHECK-LABEL: @caller(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RC_I:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[RC_I]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]])
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; CHECK-NEXT: store i32 0, i32* [[RC_I]], align 4
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; CHECK-NEXT: switch i32 [[C:%.*]], label [[SW_DEFAULT_I:%.*]] [
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; CHECK-NEXT: i32 0, label [[CODEREPL_I:%.*]]
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; CHECK-NEXT: i32 1, label [[SW_BB1_I:%.*]]
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; CHECK-NEXT: i32 2, label [[CODEREPL1_I:%.*]]
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; CHECK-NEXT: ], !prof !31
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; CHECK: codeRepl.i:
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; CHECK-NEXT: call void @callee.1.sw.bb(i32* [[RC_I]])
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; CHECK-NEXT: br label [[CALLEE_1_EXIT:%.*]]
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; CHECK: sw.bb1.i:
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; CHECK-NEXT: store i32 2, i32* [[RC_I]], align 4
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: codeRepl1.i:
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; CHECK-NEXT: call void @callee.1.sw.bb2(i32* [[RC_I]])
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: sw.default.i:
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; CHECK-NEXT: store i32 [[C]], i32* [[RC_I]], align 4
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; CHECK-NEXT: br label [[CALLEE_1_EXIT]]
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; CHECK: callee.1.exit:
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[RC_I]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[RC_I]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP2]])
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;
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entry:
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%0 = call signext i32 @callee(i32 signext %c, i32 signext %c)
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ret i32 %0
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}
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"ProfileSummary", !2}
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!2 = !{!3, !4, !5, !6, !7, !8, !9, !10, !11, !12}
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!3 = !{!"ProfileFormat", !"InstrProf"}
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!4 = !{!"TotalCount", i64 2}
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!5 = !{!"MaxCount", i64 1000}
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!6 = !{!"MaxInternalCount", i64 1000}
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!7 = !{!"MaxFunctionCount", i64 1000}
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!8 = !{!"NumCounts", i64 4}
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!9 = !{!"NumFunctions", i64 2}
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!10 = !{!"IsPartialProfile", i64 0}
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!11 = !{!"PartialProfileRatio", double 0.000000e+00}
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!12 = !{!"DetailedSummary", !13}
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!13 = !{!14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29}
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!14 = !{i32 10000, i64 0, i32 0}
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!15 = !{i32 100000, i64 0, i32 0}
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!16 = !{i32 200000, i64 0, i32 0}
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!17 = !{i32 300000, i64 0, i32 0}
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!18 = !{i32 400000, i64 0, i32 0}
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!19 = !{i32 500000, i64 1, i32 2}
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!20 = !{i32 600000, i64 1, i32 2}
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!21 = !{i32 700000, i64 1, i32 2}
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!22 = !{i32 800000, i64 1, i32 2}
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!23 = !{i32 900000, i64 1, i32 2}
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!24 = !{i32 950000, i64 1, i32 2}
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!25 = !{i32 990000, i64 1, i32 2}
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!26 = !{i32 999000, i64 1, i32 2}
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!27 = !{i32 999900, i64 1, i32 2}
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!28 = !{i32 999990, i64 1, i32 2}
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!29 = !{i32 999999, i64 1, i32 2}
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!30 = !{!"function_entry_count", i64 1000}
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!31 = !{!"branch_weights", i32 500, i32 10, i32 150, i32 40}
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