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Updating MIR Language Reference to include new syntax for symbols and physregs.
External symbols now get the sigil '&' while physical registers get the sigil '$' for their prefix. llvm-svn: 327276
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Puyan Lotfi
parent
152d382cd4
commit
15af41a330
@ -185,15 +185,15 @@ of such YAML document:
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name: inc
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tracksRegLiveness: true
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liveins:
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- { reg: '%rdi' }
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- { reg: '$rdi' }
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body: |
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bb.0.entry:
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liveins: %rdi
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liveins: $rdi
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%eax = MOV32rm %rdi, 1, _, 0, _
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%eax = INC32r killed %eax, implicit-def dead %eflags
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MOV32mr killed %rdi, 1, _, 0, _, %eax
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RETQ %eax
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$eax = MOV32rm $rdi, 1, _, 0, _
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$eax = INC32r killed $eax, implicit-def dead $eflags
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MOV32mr killed $rdi, 1, _, 0, _, $eax
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RETQ $eax
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...
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The document above consists of attributes that represent the various
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@ -307,7 +307,7 @@ the instructions:
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.. code-block:: text
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bb.0.entry:
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liveins: %edi, %esi
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liveins: $edi, $esi
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The list of live in registers and successors can be empty. The language also
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allows multiple live in register and successor lists - they are combined into
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@ -344,7 +344,7 @@ operand:
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.. code-block:: text
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RETQ %eax
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RETQ $eax
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However, if the machine instruction has one or more explicitly defined register
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operands, the instruction's name has to be specified after them. The example
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@ -353,7 +353,7 @@ defined register operands:
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.. code-block:: text
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%sp, %fp, %lr = LDPXpost %sp, 2
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$sp, $fp, $lr = LDPXpost $sp, 2
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The instruction names are serialized using the exact definitions from the
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target's ``*InstrInfo.td`` files, and they are case sensitive. This means that
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@ -370,11 +370,11 @@ instruction's name:
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.. code-block:: text
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%fp = frame-setup ADDXri %sp, 0, 0
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$fp = frame-setup ADDXri $sp, 0, 0
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.. code-block:: text
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%x21, %x20 = frame-destroy LDPXi %sp
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$x21, $x20 = frame-destroy LDPXi $sp
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.. _registers:
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@ -385,9 +385,9 @@ The syntax for bundled instructions is the following:
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.. code-block:: text
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BUNDLE implicit-def %r0, implicit-def %r1, implicit %r2 {
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%r0 = SOME_OP %r2
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%r1 = ANOTHER_OP internal %r0
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BUNDLE implicit-def $r0, implicit-def $r1, implicit $r2 {
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$r0 = SOME_OP $r2
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$r1 = ANOTHER_OP internal $r0
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}
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The first instruction is often a bundle header. The instructions between ``{``
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@ -402,23 +402,23 @@ serialization language. They are primarly used in the
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but they can also be used in a number of other places, like the
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:ref:`basic block's live in list <bb-liveins>`.
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The physical registers are identified by their name. They use the following
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syntax:
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The physical registers are identified by their name and by the '$' prefix sigil.
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They use the following syntax:
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.. code-block:: text
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%<name>
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$<name>
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The example below shows three X86 physical registers:
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.. code-block:: text
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%eax
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%r15
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%eflags
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$eax
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$r15
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$eflags
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The virtual registers are identified by their ID number. They use the following
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syntax:
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The virtual registers are identified by their ID number and by the '%' sigil.
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They use the following syntax:
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.. code-block:: text
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@ -431,7 +431,7 @@ Example:
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%0
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The null registers are represented using an underscore ('``_``'). They can also be
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represented using a '``%noreg``' named register, although the former syntax
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represented using a '``$noreg``' named register, although the former syntax
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is preferred.
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.. _machine-operands:
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@ -452,7 +452,7 @@ immediate machine operand ``-42``:
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.. code-block:: text
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%eax = MOV32ri -42
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$eax = MOV32ri -42
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An immediate operand is also used to represent a subregister index when the
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machine instruction has one of the following opcodes:
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@ -510,7 +510,7 @@ This example shows an instance of the X86 ``XOR32rr`` instruction that has
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.. code-block:: text
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dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
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dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
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.. _register-flags:
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@ -630,7 +630,7 @@ a global value operand named ``G``:
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.. code-block:: text
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%rax = MOV64rm %rip, 1, _, @G, _
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$rax = MOV64rm $rip, 1, _, @G, _
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The named global values are represented using an identifier with the '@' prefix.
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If the identifier doesn't match the regular expression
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@ -652,7 +652,7 @@ and the offset 8:
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.. code-block:: text
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%sgpr2 = S_ADD_U32 _, target-index(amdgpu-constdata-start) + 8, implicit-def _, implicit-def _
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$sgpr2 = S_ADD_U32 _, target-index(amdgpu-constdata-start) + 8, implicit-def _, implicit-def _
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Jump-table Index Operands
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^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -661,7 +661,7 @@ A jump-table index operand with the index 0 is printed as following:
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.. code-block:: text
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tBR_JTr killed %r0, %jump-table.0
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tBR_JTr killed $r0, %jump-table.0
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A machine jump-table entry contains a list of ``MachineBasicBlocks``. When serializing all the function's jump-table entries, the following format is used:
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@ -690,7 +690,7 @@ Example:
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External Symbol Operands
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^^^^^^^^^^^^^^^^^^^^^^^^^
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An external symbol operand is represented using an identifier with the ``$``
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An external symbol operand is represented using an identifier with the ``&``
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prefix. The identifier is surrounded with ""'s and escaped if it has any
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special non-printable characters in it.
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@ -698,7 +698,7 @@ Example:
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.. code-block:: text
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CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
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CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
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MCSymbol Operands
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^^^^^^^^^^^^^^^^^
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@ -725,7 +725,7 @@ The syntax is:
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.. code-block:: text
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CFI_INSTRUCTION offset %w30, -16
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CFI_INSTRUCTION offset $w30, -16
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which may be emitted later in the MC layer as:
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@ -742,7 +742,7 @@ The syntax for the ``returnaddress`` intrinsic is:
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.. code-block:: text
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%x0 = COPY intrinsic(@llvm.returnaddress)
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$x0 = COPY intrinsic(@llvm.returnaddress)
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Predicate Operands
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^^^^^^^^^^^^^^^^^^
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