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[X86][MMX] Added custom lowering action for MMX SELECT (PR30418)
Fix for pr30418 - error in backend: Cannot select: t17: x86mmx = select_cc t2, Constant:i64<0>, t7, t8, seteq:ch Differential Revision: https://reviews.llvm.org/D34661 llvm-svn: 309614
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@ -419,6 +419,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SELECT, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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}
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// Custom action for SELECT MMX and expand action for SELECT_CC MMX
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setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand);
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setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
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// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
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// SjLj exception handling but a light-weight setjmp/longjmp replacement to
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@ -30631,6 +30636,14 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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return SDValue(N, 0);
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}
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// Custom action for SELECT MMX
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if (VT == MVT::x86mmx) {
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LHS = DAG.getBitcast(MVT::i64, LHS);
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RHS = DAG.getBitcast(MVT::i64, RHS);
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SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS);
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return DAG.getBitcast(VT, newSelect);
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}
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return SDValue();
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}
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120
test/CodeGen/X86/select-mmx.ll
Normal file
120
test/CodeGen/X86/select-mmx.ll
Normal file
@ -0,0 +1,120 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=X64
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; RUN: llc -mtriple=i686-unknown-unknown -mattr=+mmx < %s | FileCheck %s --check-prefix=I32
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; From source: clang -02
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;__m64 test47(int a)
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;{
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; __m64 x = (a)? (__m64)(7): (__m64)(0);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test47(i64 %arg) {
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;
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; X64-LABEL: test47:
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; X64: # BB#0:
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: movl $7, %ecx
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; X64-NEXT: cmoveq %rcx, %rax
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; X64-NEXT: movd %rax, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movd %mm0, %rax
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; X64-NEXT: retq
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;
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; I32-LABEL: test47:
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; I32: # BB#0:
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; I32-NEXT: pushl %ebp
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; I32-NEXT: .Lcfi0:
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; I32-NEXT: .cfi_def_cfa_offset 8
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; I32-NEXT: .Lcfi1:
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; I32-NEXT: .cfi_offset %ebp, -8
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; I32-NEXT: movl %esp, %ebp
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; I32-NEXT: .Lcfi2:
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; I32-NEXT: .cfi_def_cfa_register %ebp
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; I32-NEXT: andl $-8, %esp
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; I32-NEXT: subl $16, %esp
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; I32-NEXT: movl 8(%ebp), %eax
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; I32-NEXT: orl 12(%ebp), %eax
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; I32-NEXT: movl $7, %eax
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; I32-NEXT: je .LBB0_2
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; I32-NEXT: # BB#1:
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; I32-NEXT: xorl %eax, %eax
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; I32-NEXT: .LBB0_2:
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; I32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; I32-NEXT: movl $0, {{[0-9]+}}(%esp)
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; I32-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; I32-NEXT: psllw %mm0, %mm0
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; I32-NEXT: movq %mm0, (%esp)
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; I32-NEXT: movl (%esp), %eax
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; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; I32-NEXT: movl %ebp, %esp
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; I32-NEXT: popl %ebp
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; I32-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%slct = select i1 %cond, x86_mmx bitcast (i64 7 to x86_mmx), x86_mmx bitcast (i64 0 to x86_mmx)
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%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
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%retc = bitcast x86_mmx %psll to i64
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ret i64 %retc
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}
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; From source: clang -O2
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;__m64 test49(int a, long long n, long long m)
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;{
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; __m64 x = (a)? (__m64)(n): (__m64)(m);
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; return __builtin_ia32_psllw(x, x);
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;}
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define i64 @test49(i64 %arg, i64 %x, i64 %y) {
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;
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; X64-LABEL: test49:
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; X64: # BB#0:
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; X64-NEXT: testq %rdi, %rdi
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; X64-NEXT: cmovneq %rdx, %rsi
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; X64-NEXT: movd %rsi, %mm0
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; X64-NEXT: psllw %mm0, %mm0
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; X64-NEXT: movd %mm0, %rax
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; X64-NEXT: retq
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;
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; I32-LABEL: test49:
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; I32: # BB#0:
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; I32-NEXT: pushl %ebp
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; I32-NEXT: .Lcfi3:
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; I32-NEXT: .cfi_def_cfa_offset 8
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; I32-NEXT: .Lcfi4:
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; I32-NEXT: .cfi_offset %ebp, -8
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; I32-NEXT: movl %esp, %ebp
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; I32-NEXT: .Lcfi5:
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; I32-NEXT: .cfi_def_cfa_register %ebp
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; I32-NEXT: andl $-8, %esp
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; I32-NEXT: subl $8, %esp
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; I32-NEXT: movl 8(%ebp), %eax
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; I32-NEXT: orl 12(%ebp), %eax
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; I32-NEXT: je .LBB1_1
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; I32-NEXT: # BB#2:
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; I32-NEXT: leal 24(%ebp), %eax
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; I32-NEXT: jmp .LBB1_3
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; I32-NEXT: .LBB1_1:
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; I32-NEXT: leal 16(%ebp), %eax
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; I32-NEXT: .LBB1_3:
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; I32-NEXT: movq (%eax), %mm0
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; I32-NEXT: psllw %mm0, %mm0
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; I32-NEXT: movq %mm0, (%esp)
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; I32-NEXT: movl (%esp), %eax
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; I32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; I32-NEXT: movl %ebp, %esp
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; I32-NEXT: popl %ebp
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; I32-NEXT: retl
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%cond = icmp eq i64 %arg, 0
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%xmmx = bitcast i64 %x to x86_mmx
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%ymmx = bitcast i64 %y to x86_mmx
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%slct = select i1 %cond, x86_mmx %xmmx, x86_mmx %ymmx
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%psll = tail call x86_mmx @llvm.x86.mmx.psll.w(x86_mmx %slct, x86_mmx %slct)
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%retc = bitcast x86_mmx %psll to i64
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ret i64 %retc
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}
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declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx)
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