mirror of
https://github.com/RPCS3/llvm-mirror.git
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[PowerPC] Materialize more constants with CR-field set in late peephole
Revision r322373 fixed a bug in how we materialize constants when the CR-field needs to be set. However the fix is overly conservative. It will only do the transform if AND-ing the input with the new constant produces the same new constant. This is of course correct, but not necessarily required. If there are no futher uses of the constant, the constant can be changed. If there are no uses of the GPR result, the final result of the materialization isn't important other than it needs to compare to zero correctly (lt, gt, eq). Differential revision: https://reviews.llvm.org/D42109 llvm-svn: 337008
This commit is contained in:
Nemanja Ivanovic
parent
9249622410
commit
165362eb26
@ -2480,8 +2480,6 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc != PPC::RLDICL_32;
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NewImm = InVal.getSExtValue();
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SetCR = Opc == PPC::RLDICLo;
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if (SetCR && (SExtImm & NewImm) != NewImm)
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return false;
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break;
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}
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return false;
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@ -2495,7 +2493,7 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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int64_t ME = MI.getOperand(4).getImm();
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APInt InVal(32, SExtImm, true);
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InVal = InVal.rotl(SH);
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// Set the bits ( MB + 32 ) to ( ME + 32 ).
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// Set the bits ( MB + 32 ) to ( ME + 32 ).
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uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
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InVal &= Mask;
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// Can't replace negative values with an LI as that will sign-extend
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@ -2509,8 +2507,6 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
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NewImm = InVal.getSExtValue();
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SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
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if (SetCR && (SExtImm & NewImm) != NewImm)
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return false;
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break;
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}
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return false;
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@ -2536,6 +2532,33 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
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}
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if (ReplaceWithLI) {
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// We need to be careful with CR-setting instructions we're replacing.
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if (SetCR) {
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// We don't know anything about uses when we're out of SSA, so only
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// replace if the new immediate will be reproduced.
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bool ImmChanged = (SExtImm & NewImm) != NewImm;
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if (PostRA && ImmChanged)
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return false;
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if (!PostRA) {
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// If the defining load-immediate has no other uses, we can just replace
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// the immediate with the new immediate.
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if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
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DefMI->getOperand(1).setImm(NewImm);
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// If we're not using the GPR result of the CR-setting instruction, we
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// just need to and with zero/non-zero depending on the new immediate.
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else if (MRI->use_empty(MI.getOperand(0).getReg())) {
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if (NewImm) {
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assert(Immediate && "Transformation converted zero to non-zero?");
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NewImm = Immediate;
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}
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}
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else if (ImmChanged)
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return false;
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}
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}
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LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
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LLVM_DEBUG(MI.dump());
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LLVM_DEBUG(dbgs() << "Fed by:\n");
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@ -3982,7 +3982,8 @@ body: |
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%1 = COPY $x4
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%0 = LI8 200
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%2 = RLDICLo %0, 61, 3, implicit-def $cr0
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; CHECK-NOT: ANDI
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; CHECK: LI8 25
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; CHECK: ANDIo8 %0, 25
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; CHECK-LATE-NOT: andi.
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%3 = COPY killed $cr0
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%4 = ISEL8 %1, %2, %3.sub_eq
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@ -4298,7 +4299,8 @@ body: |
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%2 = COPY %1.sub_32
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%3 = LI -22
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%4 = RLWINMo %3, 0, 24, 31, implicit-def $cr0
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; CHECK: ANDIo %3, 234
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; CHECK: LI -22
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; CHECK: ANDIo %3, 65514
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; CHECK-LATE: li 3, -22
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; CHECK-LATE: andi. 5, 3, 234
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%5 = COPY killed $cr0
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@ -4362,7 +4364,8 @@ body: |
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%2 = COPY %1.sub_32
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%3 = LI -22
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%4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
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; CHECK-NOT: ANDI
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; CHECK: LI -22
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; CHECK-NOT: ANDIo8 %3, 65514
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; CHECK-LATE-NOT: andi.
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%5 = COPY killed $cr0
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%6 = ISEL %2, %3, %5.sub_eq
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416
test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
Normal file
416
test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
Normal file
@ -0,0 +1,416 @@
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# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
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# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE
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--- |
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; ModuleID = 'rlwinm_rldicl_to_andi.ll'
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source_filename = "rlwinm_rldicl_to_andi.c"
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMSingleUseDef(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMNoGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMNoGPRUseNonZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLSingleUseDef(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLNoGPRUseZero(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLNoGPRUseNonZero(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"PIC Level", i32 2}
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!2 = !{!"clang version 7.0.0 (trunk 322378)"}
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...
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---
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name: testRLWINMSingleUseDef
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# CHECK: testRLWINMSingleUseDef
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# CHECK-LATE: testRLWINMSingleUseDef
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc = LI -11
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%4:gprc_and_gprc_nor0 = RLWINMo %3, 2, 20, 31, implicit-def $cr0
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; CHECK: LI 4055
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; CHECK: ANDIo %3, 4055
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rlwinm.
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %4, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLWINMNoGPRUseZero
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc_and_gprc_nor0 = LI 1
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%4:gprc = RLWINMo %3, 21, 20, 31, implicit-def $cr0
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; CHECK: LI 1
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; CHECK: ANDIo %3, 0
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; CHECK-LATE: li [[IMM:[0-9]+]], 1
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; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %3, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLWINMNoGPRUseNonZero
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc_and_gprc_nor0 = LI -11
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%4:gprc = RLWINMo %3, 2, 20, 31, implicit-def $cr0
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; CHECK: LI -11
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; CHECK: ANDIo %3, 65525
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rlwinm.
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %3, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLDICLSingleUseDef
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 3, class: crrc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc_and_g8rc_nox0 = COPY $x4
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%0:g8rc = LI8 -11
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%2:g8rc_and_g8rc_nox0 = RLDICLo %0, 2, 49, implicit-def $cr0
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; CHECK: LI8 32727
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; CHECK: ANDIo8 %0, 32727
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rldicl.
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%3:crrc = COPY killed $cr0
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||||
%4:g8rc = ISEL8 %2, %1, %3.sub_eq
|
||||
$x3 = COPY %4
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
...
|
||||
---
|
||||
name: testRLDICLNoGPRUseZero
|
||||
alignment: 4
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
|
||||
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
|
||||
- { id: 2, class: g8rc, preferred-register: '' }
|
||||
- { id: 3, class: crrc, preferred-register: '' }
|
||||
- { id: 4, class: g8rc, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$x3', virtual-reg: '%0' }
|
||||
- { reg: '$x4', virtual-reg: '%1' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 4294967295
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x3, $x4
|
||||
|
||||
%1:g8rc_and_g8rc_nox0 = COPY $x4
|
||||
%0:g8rc_and_g8rc_nox0 = LI8 1
|
||||
%2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0
|
||||
; CHECK: LI8 1
|
||||
; CHECK: ANDIo8 %0, 0
|
||||
; CHECK-LATE: li [[IMM:[0-9]+]], 1
|
||||
; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
|
||||
%3:crrc = COPY killed $cr0
|
||||
%4:g8rc = ISEL8 %0, %1, %3.sub_eq
|
||||
$x3 = COPY %4
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
...
|
||||
---
|
||||
name: testRLDICLNoGPRUseNonZero
|
||||
alignment: 4
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
|
||||
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
|
||||
- { id: 2, class: g8rc, preferred-register: '' }
|
||||
- { id: 3, class: crrc, preferred-register: '' }
|
||||
- { id: 4, class: g8rc, preferred-register: '' }
|
||||
liveins:
|
||||
- { reg: '$x3', virtual-reg: '%0' }
|
||||
- { reg: '$x4', virtual-reg: '%1' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 4294967295
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $x3, $x4
|
||||
|
||||
%1:g8rc_and_g8rc_nox0 = COPY $x4
|
||||
%0:g8rc_and_g8rc_nox0 = LI8 -11
|
||||
%2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0
|
||||
; CHECK: LI8 -11
|
||||
; CHECK: ANDIo8 %0, 65525
|
||||
; CHECK-LATE-NOT: andi.
|
||||
; CHECK-LATE: rldicl.
|
||||
%3:crrc = COPY killed $cr0
|
||||
%4:g8rc = ISEL8 %0, %1, %3.sub_eq
|
||||
$x3 = COPY %4
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user