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This patch addresses a problem with the Post RA scheduler generating an

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incorrect instruction sequence due to it not being aware that an
inline assembly instruction may reference memory.

This patch fixes the problem by causing the scheduler to always assume that any
inline assembly code instruction could access memory. This is necessary because
the internal representation of the inline instruction does not include
any information about memory accesses.
 
This should fix PR13504.

llvm-svn: 166929
This commit is contained in:
Preston Gurd 2012-10-29 15:01:23 +00:00
parent 2682b73f6d
commit 1683865eea
2 changed files with 18 additions and 0 deletions
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5
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -420,6 +420,11 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
/// Return true if MI is an instruction we are unable to reason about
/// (like a call or something with unmodeled side effects).
static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
if (MI->isInlineAsm()) {
// Until we can tell if an inline assembly instruction accesses
// memory, we must assume all such instructions do so.
return true;
}
if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
(MI->hasOrderedMemoryRef() &&
(!MI->mayLoad() || !MI->isInvariantLoad(AA))))

13
test/CodeGen/X86/inlineasm-sched-bug.ll Normal file
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@ -0,0 +1,13 @@
; PR13504
; RUN: llc -march=x86 -mcpu=atom <%s | FileCheck %s
; CHECK: bsfl
; CHECK-NOT: movl
define i32 @foo(i32 %treemap) nounwind uwtable {
entry:
%sub = sub i32 0, %treemap
%and = and i32 %treemap, %sub
%0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind
ret i32 %0
}