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[x86] Update this test to run a full complement of the ISA extensions,
and use the new grouped FileCheck patterns to match them. No interesting changes yet, but this test is now in proper form to have the other shuffle combining tests merged into it. llvm-svn: 218857
This commit is contained in:
Chandler Carruth
parent
d38853bc15
commit
16ffa749c8
@ -1,4 +1,8 @@
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; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK-SSE2
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; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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;
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; Verify that the DAG combiner correctly folds bitwise operations across
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; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
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@ -12,57 +16,72 @@ declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
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declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
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define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd1
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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%c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
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; ALL-LABEL: combine_pshufd1:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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%c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
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ret <4 x i32> %c
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}
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define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd2
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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; ALL-LABEL: combine_pshufd2:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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%b.cast = bitcast <4 x i32> %b to <8 x i16>
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
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%c.cast = bitcast <8 x i16> %c to <4 x i32>
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
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ret <4 x i32> %d
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}
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define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd3
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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; ALL-LABEL: combine_pshufd3:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
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%b.cast = bitcast <4 x i32> %b to <8 x i16>
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
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%c.cast = bitcast <8 x i16> %c to <4 x i32>
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
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ret <4 x i32> %d
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}
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define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd4
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; CHECK-SSE2-NEXT: retq
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
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; SSE-LABEL: combine_pshufd4:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufd4:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; AVX-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
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%b.cast = bitcast <4 x i32> %b to <8 x i16>
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
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%c.cast = bitcast <8 x i16> %c to <4 x i32>
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
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%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
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ret <4 x i32> %d
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}
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define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd5
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; CHECK-SSE2-NEXT: retq
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
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; SSE-LABEL: combine_pshufd5:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufd5:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; AVX-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
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%b.cast = bitcast <4 x i32> %b to <8 x i16>
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
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%c.cast = bitcast <8 x i16> %c to <4 x i32>
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@ -71,53 +90,72 @@ define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
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}
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define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufd6
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshufd $0
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; CHECK-SSE2-NEXT: retq
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; SSE-LABEL: combine_pshufd6:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufd6:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; AVX-NEXT: retq
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entry:
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%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
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%c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
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ret <4 x i32> %c
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}
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define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw1
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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; ALL-LABEL: combine_pshuflw1:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: retq
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entry:
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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ret <8 x i16> %c
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}
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define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw2
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: retq
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; ALL-LABEL: combine_pshuflw2:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: retq
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entry:
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshuflw3
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshufhw {{.*}} # xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; CHECK-SSE2-NEXT: retq
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; SSE-LABEL: combine_pshuflw3:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshuflw3:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
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; AVX-NEXT: retq
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entry:
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%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
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; CHECK-SSE2-LABEL: @combine_pshufhw1
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; CHECK-SSE2: # BB#0:
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; CHECK-SSE2-NEXT: pshuflw {{.*}} # xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; CHECK-SSE2-NEXT: retq
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; SSE-LABEL: combine_pshufhw1:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_pshufhw1:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
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; AVX-NEXT: retq
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entry:
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%b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
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%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
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%d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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