[AVR] Include AVR by default in LLVM builds

Summary:
This patch makes the AVR backend an official target of LLVM, serving
as a request for comments for moving the AVR backend out of
experimental.

A future patch will move the LLVM AVR buildbot (llvm-avr-linux) from the
staging buildmaster to the production buildmaster, so error emails will
start to go out.

Summary of the backend
----------------------

  - 16-bit little endian
  - AsmParser based assembly parser
  - uses the MC library for generating AVR ELFs
  - most logic driven from standard TableGen-erated tables like other
    backends
  - passes all of the test suite under `check-all`, including generic
    CodeGen and DebugInfo tests
  - Used in two frontends
  - Limited, but functional support for DebugInfo and LLVM DWARF dumping
  - Binary compatible with AVR-GCC and avr-{libc,libgcc} for the most part
  - Cannot lower 32-bit shifts due to a bug, can lower shifts larger or
    smaller
  - Supports assembly/MC for all the entire AVR ISA, generally generates poorly
    optimized machine instructions, with most focus thus far on correctness

I've added reviewers and subscribers from previous patches where backends were made official,
and those who participated in the recent thread on llvm-dev, please add anybody I've missed.

The most recent discussion on this topic can be found in the llvm-dev thread [Moving the AVR backend out of experimental](https://lists.llvm.org/pipermail/llvm-dev/2020-February/139158.html)

Reviewers: chandlerc, lattner, rengolin, tstellar, arsenm, thakis, simoll, asb

Reviewed By: rengolin, thakis

Subscribers: CryZe, wdng, mgorny, aprantl, Jim, hans, aykevl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75099

CMakeLists.txt

@@ -289,6 +289,7 @@ set(LLVM_ALL_TARGETS
   AArch64
   AMDGPU
   ARM
+  AVR
   BPF
   Hexagon
   Lanai