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Fix pattern match for movi with 0D result

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Patch by Jiangning Liu.

With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.

llvm-svn: 196806
This commit is contained in:
Ana Pazos 2013-12-09 19:29:14 +00:00
parent f16c4f730c
commit 171fb9a9de
3 changed files with 24 additions and 3 deletions
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5
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -1437,9 +1437,8 @@ let isReMaterializable = 1 in {
def MOVIdi : NeonI_1VModImm<0b0, 0b1,
(outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
"movi\t $Rd, $Imm",
[(set (f64 FPR64:$Rd),
(f64 (bitconvert
(v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
[(set (v1i64 FPR64:$Rd),
(v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
NoItinerary> {
let cmode = 0b1110;
}

10
test/CodeGen/AArch64/neon-aba-abd.ll
View File

@ -157,6 +157,16 @@ define <2 x i32> @test_sabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
ret <2 x i32> %abd
}
define <2 x i32> @test_sabd_v2i32_const() {
; CHECK: test_sabd_v2i32_const:
; CHECK: movi d1, #0xffffffff0000
; CHECK-NEXT: sabd v0.2s, v0.2s, v1.2s
%1 = tail call <2 x i32> @llvm.arm.neon.vabds.v2i32(
<2 x i32> <i32 -2147483648, i32 2147450880>,
<2 x i32> <i32 -65536, i32 65535>)
ret <2 x i32> %1
}
define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; CHECK: test_saba_v2i32:
%abd = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)

12
test/CodeGen/AArch64/neon-mov.ll
View File

@ -202,4 +202,16 @@ define <2 x double> @fmov2d() {
ret <2 x double> < double -1.2e1, double -1.2e1>
}
define <2 x i32> @movi1d_1() {
; CHECK: movi d0, #0xffffffff0000
ret <2 x i32> < i32 -65536, i32 65535>
}
declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
define <2 x i32> @movi1d() {
; CHECK: movi d1, #0xffffffff0000
%1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
ret <2 x i32> %1
}