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Modify MipsFrameLowering::emitPrologue and emitEpilogue.
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. llvm-svn: 148917
This commit is contained in:
Akira Hatanaka
parent
9a829c1762
commit
175341c860
@ -11,6 +11,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "MipsAnalyzeImmediate.h"
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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@ -93,47 +94,40 @@ bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
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return true;
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}
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static unsigned AlignOffset(unsigned Offset, unsigned Align) {
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return (Offset + Align - 1) / Align * Align;
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}
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// expand pair of register and immediate if the immediate doesn't fit in the
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// 16-bit offset field.
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// e.g.
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// if OrigImm = 0x10000, OrigReg = $sp:
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// generate the following sequence of instrs:
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// lui $at, hi(0x10000)
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// addu $at, $sp, $at
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//
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// (NewReg, NewImm) = ($at, lo(Ox10000))
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// return true
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static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
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unsigned& NewReg, int& NewImm,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator I) {
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// OrigImm fits in the 16-bit field
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if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
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NewReg = OrigReg;
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NewImm = OrigImm;
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return false;
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}
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MachineFunction* MF = MBB.getParent();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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DebugLoc DL = I->getDebugLoc();
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int ImmLo = (short)(OrigImm & 0xffff);
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int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
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((OrigImm & 0x8000) != 0);
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// Build an instruction sequence to load an immediate that is too large to fit
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// in 16-bit and add the result to Reg.
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static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64,
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const MipsInstrInfo &TII, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator II, DebugLoc DL) {
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unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
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unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu;
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unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
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MipsAnalyzeImmediate AnalyzeImm;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
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BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
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BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
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.addReg(Mips::AT);
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NewReg = Mips::AT;
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NewImm = ImmLo;
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BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
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return true;
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == LUi)
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BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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else
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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// Build the remaining instructions in Seq.
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for (++Inst; Inst != Seq.end(); ++Inst)
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg);
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BuildMI(MBB, II, DL, TII.get(Mips::ATMACRO));
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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@ -142,14 +136,12 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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MachineRegisterInfo& MRI = MF.getRegInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
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unsigned NewReg = 0;
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int NewImm = 0;
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bool ATUsed;
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unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP;
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unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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@ -165,33 +157,23 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ?
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(MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
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MipsFI->getMaxCallFrameSize();
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unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
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AlignOffset(MFI->getStackSize(), StackAlign);
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uint64_t StackSize = RoundUpToAlignment(LocalVarAreaOffset, StackAlign) +
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RoundUpToAlignment(MFI->getStackSize(), StackAlign);
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// Update stack size
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MFI->setStackSize(StackSize);
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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// Emit instructions that set $gp using the the value of $t9.
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// O32 uses the directive .cpload while N32/64 requires three instructions to
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// do this.
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// TODO: Do not emit these instructions if no instructions use $gp.
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if (isPIC && STI.isABI_O32())
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BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::CPLOAD))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
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.addReg(RegInfo->getPICCallReg());
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else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) {
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// lui $28,%hi(%neg(%gp_rel(fname)))
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// addu $28,$28,$25
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// addiu $28,$28,%lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, MBBI, dl, TII.get(LUi), GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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}
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BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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@ -200,13 +182,11 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack : addi sp, sp, (-imm)
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ATUsed = expandRegLargeImmPair(SP, -StackSize, NewReg, NewImm, MBB, MBBI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
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// FIXME: change this when mips goes MC".
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if (ATUsed)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
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// Adjust stack.
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if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize)
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
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else // Expand immediate that doesn't fit in 16-bit.
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expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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@ -259,6 +239,21 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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}
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if ((STI.isABI_N64() || (isPIC && STI.isABI_N32())) &&
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MRI.isPhysRegUsed(GP)) {
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// lui $28,%hi(%neg(%gp_rel(fname)))
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// addu $28,$28,$25
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// addiu $28,$28,%lo(%neg(%gp_rel(fname)))
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MachineBasicBlock::iterator InsPos = llvm::prior(MBBI);
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, MBBI, dl, TII.get(LUi), GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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MBBI = ++InsPos;
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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@ -298,13 +293,6 @@ void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// Get the number of bytes from FrameInfo
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unsigned StackSize = MFI->getStackSize();
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unsigned NewReg = 0;
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int NewImm = 0;
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bool ATUsed = false;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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@ -317,15 +305,17 @@ void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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}
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// adjust stack : insert addi sp, sp, (imm)
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if (StackSize) {
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ATUsed = expandRegLargeImmPair(SP, StackSize, NewReg, NewImm, MBB, MBBI);
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(NewReg).addImm(NewImm);
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// Get the number of bytes from FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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// FIXME: change this when mips goes MC".
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if (ATUsed)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
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}
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if (!StackSize)
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return;
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// Adjust stack.
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if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize)
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
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else // Expand immediate that doesn't fit in 16-bit.
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expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
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}
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void MipsFrameLowering::
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@ -7,8 +7,8 @@
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define void @f() nounwind {
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entry:
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; CHECK: lui $at, 65534
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; CHECK: addu $at, $sp, $at
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; CHECK: addiu $sp, $at, -24
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; CHECK: addiu $at, $at, -24
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; CHECK: addu $sp, $sp, $at
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; CHECK: .cprestore 65536
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%agg.tmp = alloca %struct.S1, align 1
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