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[InstCombine] move add after umin/umax
In the motivating cases from PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 ...moving the add enables us to narrow the min/max which eliminates zext/trunc which enables signficantly better vectorization. But that bug is still not completely fixed. https://rise4fun.com/Alive/5KQ Name: umax Pre: C1 u>= C0 %a = add nuw i8 %x, C0 %cond = icmp ugt i8 %a, C1 %r = select i1 %cond, i8 %a, i8 C1 => %c2 = icmp ugt i8 %x, C1-C0 %u2 = select i1 %c2, i8 %x, i8 C1-C0 %r = add nuw i8 %u2, C0 Name: umin Pre: C1 u>= C0 %a = add nuw i32 %x, C0 %cond = icmp ult i32 %a, C1 %r = select i1 %cond, i32 %a, i32 C1 => %c2 = icmp ult i32 %x, C1-C0 %u2 = select i1 %c2, i32 %x, i32 C1-C0 %r = add nuw i32 %u2, C0 llvm-svn: 355221
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@ -1563,6 +1563,30 @@ static Instruction *foldSelectCmpXchg(SelectInst &SI) {
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return nullptr;
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}
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static Instruction *moveAddAfterMinMax(SelectPatternFlavor SPF, Value *X,
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Value *Y,
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InstCombiner::BuilderTy &Builder) {
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assert (SelectPatternResult::isMinOrMax(SPF) && "Expected min/max pattern");
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bool IsUnsigned = SPF == SelectPatternFlavor::SPF_UMIN ||
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SPF == SelectPatternFlavor::SPF_UMAX;
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// TODO: If InstSimplify could fold all cases where C2 <= C1, we could change
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// the constant value check to an assert.
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Value *A;
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const APInt *C1, *C2;
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if (IsUnsigned && match(X, m_NUWAdd(m_Value(A), m_APInt(C1))) &&
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match(Y, m_APInt(C2)) && C2->uge(*C1) && X->hasNUses(2)) {
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// umin (add nuw A, C1), C2 --> add nuw (umin A, C2 - C1), C1
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// umax (add nuw A, C1), C2 --> add nuw (umax A, C2 - C1), C1
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Value *NewMinMax = createMinMax(Builder, SPF, A,
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ConstantInt::get(X->getType(), *C2 - *C1));
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return BinaryOperator::CreateNUW(BinaryOperator::Add, NewMinMax,
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ConstantInt::get(X->getType(), *C1));
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}
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// TODO: Handle SMIN/SMAX (similar to unsigned, but the signed subtraction of
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// the constants must not overflow).
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return nullptr;
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}
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/// Reduce a sequence of min/max with a common operand.
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static Instruction *factorizeMinMaxTree(SelectPatternFlavor SPF, Value *LHS,
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Value *RHS,
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@ -1962,6 +1986,9 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
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if (Instruction *I = moveNotAfterMinMax(RHS, LHS))
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return I;
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if (Instruction *I = moveAddAfterMinMax(SPF, LHS, RHS, Builder))
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return I;
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if (Instruction *I = factorizeMinMaxTree(SPF, LHS, RHS, Builder))
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return I;
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}
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@ -909,9 +909,9 @@ define float @not_min_of_min(i8 %i, float %x) {
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define i32 @add_umin(i32 %x) {
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; CHECK-LABEL: @add_umin(
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; CHECK-NEXT: [[A:%.*]] = add nuw i32 [[X:%.*]], 15
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], 42
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 42
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], 27
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 27
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; CHECK-NEXT: [[R:%.*]] = add nuw nsw i32 [[TMP2]], 15
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a = add nuw i32 %x, 15
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@ -922,9 +922,8 @@ define i32 @add_umin(i32 %x) {
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define i32 @add_umin_constant_limit(i32 %x) {
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; CHECK-LABEL: @add_umin_constant_limit(
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; CHECK-NEXT: [[A:%.*]] = add nuw i32 [[X:%.*]], 41
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], 42
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A]], i32 42
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
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; CHECK-NEXT: [[R:%.*]] = select i1 [[TMP1]], i32 41, i32 42
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; CHECK-NEXT: ret i32 [[R]]
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;
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%a = add nuw i32 %x, 41
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@ -1008,9 +1007,9 @@ define i32 @add_umin_extra_use(i32 %x, i32* %p) {
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define <2 x i16> @add_umin_vec(<2 x i16> %x) {
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; CHECK-LABEL: @add_umin_vec(
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; CHECK-NEXT: [[A:%.*]] = add nuw <2 x i16> [[X:%.*]], <i16 15, i16 15>
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; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i16> [[A]], <i16 240, i16 240>
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; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C]], <2 x i16> [[A]], <2 x i16> <i16 240, i16 240>
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i16> [[X:%.*]], <i16 225, i16 225>
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; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[X]], <2 x i16> <i16 225, i16 225>
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; CHECK-NEXT: [[R:%.*]] = add nuw nsw <2 x i16> [[TMP2]], <i16 15, i16 15>
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; CHECK-NEXT: ret <2 x i16> [[R]]
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;
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%a = add nuw <2 x i16> %x, <i16 15, i16 15>
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@ -1021,9 +1020,9 @@ define <2 x i16> @add_umin_vec(<2 x i16> %x) {
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define i37 @add_umax(i37 %x) {
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; CHECK-LABEL: @add_umax(
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; CHECK-NEXT: [[A:%.*]] = add nuw i37 [[X:%.*]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i37 [[A]], 42
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i37 [[A]], i37 42
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i37 [[X:%.*]], 37
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i37 [[X]], i37 37
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; CHECK-NEXT: [[R:%.*]] = add nuw i37 [[TMP2]], 5
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; CHECK-NEXT: ret i37 [[R]]
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;
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%a = add nuw i37 %x, 5
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@ -1034,9 +1033,9 @@ define i37 @add_umax(i37 %x) {
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define i37 @add_umax_constant_limit(i37 %x) {
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; CHECK-LABEL: @add_umax_constant_limit(
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; CHECK-NEXT: [[A:%.*]] = add nuw i37 [[X:%.*]], 81
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i37 [[A]], 82
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i37 [[A]], i37 82
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i37 [[X:%.*]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i37 [[X]], i37 1
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; CHECK-NEXT: [[R:%.*]] = add nuw i37 [[TMP2]], 81
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; CHECK-NEXT: ret i37 [[R]]
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;
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%a = add nuw i37 %x, 81
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@ -1050,9 +1049,7 @@ define i37 @add_umax_constant_limit(i37 %x) {
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define i37 @add_umax_simplify(i37 %x) {
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; CHECK-LABEL: @add_umax_simplify(
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; CHECK-NEXT: [[A:%.*]] = add nuw i37 [[X:%.*]], 42
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i37 [[A]], 42
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i37 [[A]], i37 42
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; CHECK-NEXT: [[R:%.*]] = add nuw i37 [[X:%.*]], 42
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; CHECK-NEXT: ret i37 [[R]]
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;
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%a = add nuw i37 %x, 42
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@ -1124,9 +1121,9 @@ define i32 @add_umax_extra_use(i32 %x, i32* %p) {
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define <2 x i33> @add_umax_vec(<2 x i33> %x) {
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; CHECK-LABEL: @add_umax_vec(
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; CHECK-NEXT: [[A:%.*]] = add nuw <2 x i33> [[X:%.*]], <i33 5, i33 5>
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; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i33> [[A]], <i33 240, i33 240>
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; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C]], <2 x i33> [[A]], <2 x i33> <i33 240, i33 240>
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i33> [[X:%.*]], <i33 235, i33 235>
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; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i33> [[X]], <2 x i33> <i33 235, i33 235>
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; CHECK-NEXT: [[R:%.*]] = add nuw <2 x i33> [[TMP2]], <i33 5, i33 5>
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; CHECK-NEXT: ret <2 x i33> [[R]]
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;
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%a = add nuw <2 x i33> %x, <i33 5, i33 5>
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@ -1137,12 +1134,10 @@ define <2 x i33> @add_umax_vec(<2 x i33> %x) {
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define i8 @PR14613_umin(i8 %x) {
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; CHECK-LABEL: @PR14613_umin(
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; CHECK-NEXT: [[U4:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[U5:%.*]] = add nuw nsw i32 [[U4]], 15
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; CHECK-NEXT: [[U6:%.*]] = icmp ult i32 [[U5]], 255
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; CHECK-NEXT: [[U7:%.*]] = select i1 [[U6]], i32 [[U5]], i32 255
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; CHECK-NEXT: [[R:%.*]] = trunc i32 [[U7]] to i8
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; CHECK-NEXT: ret i8 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], -16
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 -16
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; CHECK-NEXT: [[U7:%.*]] = add i8 [[TMP2]], 15
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; CHECK-NEXT: ret i8 [[U7]]
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;
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%u4 = zext i8 %x to i32
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%u5 = add nuw nsw i32 %u4, 15
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@ -1154,12 +1149,10 @@ define i8 @PR14613_umin(i8 %x) {
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define i8 @PR14613_umax(i8 %x) {
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; CHECK-LABEL: @PR14613_umax(
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; CHECK-NEXT: [[U4:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[U5:%.*]] = add nuw nsw i32 [[U4]], 15
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; CHECK-NEXT: [[U6:%.*]] = icmp ugt i32 [[U5]], 255
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; CHECK-NEXT: [[U7:%.*]] = select i1 [[U6]], i32 [[U5]], i32 255
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; CHECK-NEXT: [[R:%.*]] = trunc i32 [[U7]] to i8
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; CHECK-NEXT: ret i8 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], -16
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 -16
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; CHECK-NEXT: [[U7:%.*]] = add nsw i8 [[TMP2]], 15
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; CHECK-NEXT: ret i8 [[U7]]
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;
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%u4 = zext i8 %x to i32
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%u5 = add nuw nsw i32 %u4, 15
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