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Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back.
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
This commit is contained in:
James Molloy
parent
182f1c73e1
commit
17c114f241
@ -3974,7 +3974,53 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder) {
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if (!Val) return MCDisassembler::Fail;
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uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
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.getFeatureBits();
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if (FeatureBits & ARM::FeatureMClass) {
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unsigned ValLow = Val & 0xff;
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// Validate the SYSm value first.
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switch (ValLow) {
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case 0: // apsr
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case 1: // iapsr
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case 2: // eapsr
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case 3: // xpsr
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case 5: // ipsr
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case 6: // epsr
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case 7: // iepsr
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case 8: // msp
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case 9: // psp
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case 16: // primask
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case 20: // control
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break;
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case 17: // basepri
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case 18: // basepri_max
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case 19: // faultmask
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if (!(FeatureBits & ARM::HasV7Ops))
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// Values basepri, basepri_max and faultmask are only valid for v7m.
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return MCDisassembler::Fail;
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break;
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default:
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return MCDisassembler::Fail;
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}
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// The ARMv7-M architecture has an additional 2-bit mask value in the MSR
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// instruction (bits {11,10}). The mask is used only with apsr, iapsr,
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// eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates
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// if the NZCVQ bits should be moved by the instruction. Bit mask{0}
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// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
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// only if the processor includes the DSP extension.
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if ((FeatureBits & ARM::HasV7Ops) && Inst.getOpcode() == ARM::t2MSR_M) {
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unsigned Mask = (Val >> 10) & 3;
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if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
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(!(FeatureBits & ARM::FeatureDSPThumb2) && Mask == 1))
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return MCDisassembler::Fail;
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}
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} else {
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// A/R class
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if (Val == 0)
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return MCDisassembler::Fail;
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}
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Inst.addOperand(MCOperand::CreateImm(Val));
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Inst.addOperand(MCOperand::CreateImm(Val));
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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34
test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
Normal file
34
test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
Normal file
@ -0,0 +1,34 @@
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# RUN: not llvm-mc -disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 2>&1 | FileCheck %s
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#------------------------------------------------------------------------------
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# Undefined encodings for mrs
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#------------------------------------------------------------------------------
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# invalid SYSm
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
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[0xef 0xf3 0x80 0x80]
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#------------------------------------------------------------------------------
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# Undefined encodings for msr
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#------------------------------------------------------------------------------
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# invalid mask = '00'
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
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[0x80 0xf3 0x00 0x80]
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# invalid mask = '11' with SYSm not in {0..3}
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x04 0x8c]
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[0x80 0xf3 0x04 0x8c]
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# invalid mask = '01' (Cortex-M3 does not have the DSP extension)
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x00 0x84]
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[0x80 0xf3 0x00 0x84]
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# invalid SYSm
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
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[0x80 0xf3 0x80 0x88]
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@ -1,7 +1,94 @@
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m4 | FileCheck %s
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# CHECK: msr primask, r0
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#------------------------------------------------------------------------------
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0x80 0xf3 0x10 0x80
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# MRS
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#------------------------------------------------------------------------------
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# CHECK: mrs r0, primask
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# CHECK: mrs r0, apsr
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# CHECK: mrs r0, iapsr
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# CHECK: mrs r0, eapsr
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# CHECK: mrs r0, xpsr
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# CHECK: mrs r0, ipsr
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# CHECK: mrs r0, epsr
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# CHECK: mrs r0, iepsr
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# CHECK: mrs r0, msp
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# CHECK: mrs r0, psp
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# CHECK: mrs r0, primask
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# CHECK: mrs r0, basepri
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# CHECK: mrs r0, basepri_max
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# CHECK: mrs r0, faultmask
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# CHECK: mrs r0, control
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0xef 0xf3 0x00 0x80
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0xef 0xf3 0x01 0x80
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0xef 0xf3 0x02 0x80
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0xef 0xf3 0x03 0x80
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0xef 0xf3 0x05 0x80
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0xef 0xf3 0x06 0x80
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0xef 0xf3 0x07 0x80
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0xef 0xf3 0x08 0x80
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0xef 0xf3 0x09 0x80
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0xef 0xf3 0x10 0x80
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0xef 0xf3 0x10 0x80
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0xef 0xf3 0x11 0x80
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0xef 0xf3 0x12 0x80
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0xef 0xf3 0x13 0x80
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0xef 0xf3 0x14 0x80
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#------------------------------------------------------------------------------
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# MSR
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#------------------------------------------------------------------------------
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# CHECK: msr apsr, r0
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# CHECK: msr apsr_g, r0
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# CHECK: msr apsr_nzcvqg, r0
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0x80 0xf3 0x00 0x88
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0x80 0xf3 0x00 0x84
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0x80 0xf3 0x00 0x8c
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# CHECK: msr iapsr, r0
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# CHECK: msr iapsr_g, r0
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# CHECK: msr iapsr_nzcvqg, r0
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0x80 0xf3 0x01 0x88
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0x80 0xf3 0x01 0x84
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0x80 0xf3 0x01 0x8c
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# CHECK: msr eapsr, r0
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# CHECK: msr eapsr_g, r0
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# CHECK: msr eapsr_nzcvqg, r0
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0x80 0xf3 0x02 0x88
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0x80 0xf3 0x02 0x84
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0x80 0xf3 0x02 0x8c
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# CHECK: msr xpsr, r0
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# CHECK: msr xpsr_g, r0
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# CHECK: msr xpsr_nzcvqg, r0
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0x80 0xf3 0x03 0x88
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0x80 0xf3 0x03 0x84
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0x80 0xf3 0x03 0x8c
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# CHECK: msr ipsr, r0
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# CHECK: msr epsr, r0
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# CHECK: msr iepsr, r0
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# CHECK: msr msp, r0
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# CHECK: msr psp, r0
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# CHECK: msr primask, r0
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# CHECK: msr basepri, r0
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# CHECK: msr basepri_max, r0
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# CHECK: msr faultmask, r0
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# CHECK: msr control, r0
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0x80 0xf3 0x05 0x88
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0x80 0xf3 0x06 0x88
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0x80 0xf3 0x07 0x88
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0x80 0xf3 0x08 0x88
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0x80 0xf3 0x09 0x88
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0x80 0xf3 0x10 0x88
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0x80 0xf3 0x11 0x88
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0x80 0xf3 0x12 0x88
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0x80 0xf3 0x13 0x88
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0x80 0xf3 0x14 0x88
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