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https://github.com/RPCS3/llvm-mirror.git
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Use early exit to reduce indentation. No functional change.
llvm-svn: 65962
This commit is contained in:
Bob Wilson
parent
7fdda71ad7
commit
17cf012d93
@ -3171,152 +3171,152 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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APInt APSplatBits, APSplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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if (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs) &&
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SplatBitSize <= 32) {
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unsigned SplatBits = APSplatBits.getZExtValue();
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unsigned SplatUndef = APSplatUndef.getZExtValue();
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unsigned SplatSize = SplatBitSize / 8;
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if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs) || SplatBitSize > 32)
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return SDValue();
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// First, handle single instruction cases.
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unsigned SplatBits = APSplatBits.getZExtValue();
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unsigned SplatUndef = APSplatUndef.getZExtValue();
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unsigned SplatSize = SplatBitSize / 8;
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// All zeros?
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if (SplatBits == 0) {
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// Canonicalize all zero vectors to be v4i32.
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if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
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SDValue Z = DAG.getConstant(0, MVT::i32);
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Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
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Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
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}
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return Op;
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// First, handle single instruction cases.
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// All zeros?
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if (SplatBits == 0) {
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// Canonicalize all zero vectors to be v4i32.
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if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
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SDValue Z = DAG.getConstant(0, MVT::i32);
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Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
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Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
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}
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return Op;
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}
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// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
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int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
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(32-SplatBitSize));
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if (SextVal >= -16 && SextVal <= 15)
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return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
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// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
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int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
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(32-SplatBitSize));
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if (SextVal >= -16 && SextVal <= 15)
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return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
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// Two instruction sequences.
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// Two instruction sequences.
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// If this value is in the range [-32,30] and is even, use:
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// tmp = VSPLTI[bhw], result = add tmp, tmp
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if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
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SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
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Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
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// If this value is in the range [-32,30] and is even, use:
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// tmp = VSPLTI[bhw], result = add tmp, tmp
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if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
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SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
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Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
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// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
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// for fneg/fabs.
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if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
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// Make -1 and vspltisw -1:
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SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
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// Make the VSLW intrinsic, computing 0x8000_0000.
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SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
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OnesV, DAG, dl);
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// xor by OnesV to invert it.
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Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// Check to see if this is a wide variety of vsplti*, binop self cases.
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static const signed char SplatCsts[] = {
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-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
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-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
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};
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for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
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// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
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// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
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int i = SplatCsts[idx];
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// Figure out what shift amount will be used by altivec if shifted by i in
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// this splat size.
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unsigned TypeShiftAmt = i & (SplatBitSize-1);
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// vsplti + shl self.
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if (SextVal == (i << (int)TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
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Intrinsic::ppc_altivec_vslw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
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// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
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// for fneg/fabs.
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if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
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// Make -1 and vspltisw -1:
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SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
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// Make the VSLW intrinsic, computing 0x8000_0000.
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SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
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OnesV, DAG, dl);
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// xor by OnesV to invert it.
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Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
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// vsplti + srl self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
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Intrinsic::ppc_altivec_vsrw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// Check to see if this is a wide variety of vsplti*, binop self cases.
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static const signed char SplatCsts[] = {
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-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
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-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
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};
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for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
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// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
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// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
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int i = SplatCsts[idx];
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// Figure out what shift amount will be used by altivec if shifted by i in
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// this splat size.
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unsigned TypeShiftAmt = i & (SplatBitSize-1);
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// vsplti + shl self.
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if (SextVal == (i << (int)TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
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Intrinsic::ppc_altivec_vslw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// vsplti + srl self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
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Intrinsic::ppc_altivec_vsrw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// vsplti + sra self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
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Intrinsic::ppc_altivec_vsraw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// vsplti + rol self.
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if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
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((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
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Intrinsic::ppc_altivec_vrlw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// t = vsplti c, result = vsldoi t, t, 1
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if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
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}
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// t = vsplti c, result = vsldoi t, t, 2
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if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
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}
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// t = vsplti c, result = vsldoi t, t, 3
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if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
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}
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// vsplti + sra self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
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Intrinsic::ppc_altivec_vsraw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// Three instruction sequences.
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// vsplti + rol self.
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if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
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((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
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SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
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Intrinsic::ppc_altivec_vrlw
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};
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
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}
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// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
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if (SextVal >= 0 && SextVal <= 31) {
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SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
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SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
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LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
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// t = vsplti c, result = vsldoi t, t, 1
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if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
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}
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// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
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if (SextVal >= -31 && SextVal <= 0) {
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SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
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SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
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LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
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// t = vsplti c, result = vsldoi t, t, 2
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if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
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}
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// t = vsplti c, result = vsldoi t, t, 3
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if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
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SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
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return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
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}
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}
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// Three instruction sequences.
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// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
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if (SextVal >= 0 && SextVal <= 31) {
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SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
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SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
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LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
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}
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// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
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if (SextVal >= -31 && SextVal <= 0) {
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SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
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SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
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LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
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}
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return SDValue();
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