RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
Code Issues Projects Releases Wiki Activity

[SVE] Fix PromoteIntRes_TRUNCATE not to call getVectorNumElements

Browse Source 
Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D104115
This commit is contained in:
Dylan Fleming 2021-06-16 13:01:58 +01:00
parent ccc05a7e3b
commit 17f5ba8d25
2 changed files with 19 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1239,17 +1239,17 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
case TargetLowering::TypeSplitVector: {
EVT InVT = InOp.getValueType();
assert(InVT.isVector() && "Cannot split scalar types");
unsigned NumElts = InVT.getVectorNumElements();
assert(NumElts == NVT.getVectorNumElements() &&
ElementCount NumElts = InVT.getVectorElementCount();
assert(NumElts == NVT.getVectorElementCount() &&
"Dst and Src must have the same number of elements");
assert(isPowerOf2_32(NumElts) &&
assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
"Promoted vector type must be a power of two");
SDValue EOp1, EOp2;
GetSplitVector(InOp, EOp1, EOp2);
EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
NumElts/2);
NumElts.divideCoefficientBy(2));
EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);

15
test/CodeGen/AArch64/sve-trunc.ll
View File

@ -183,3 +183,18 @@ entry:
%out = trunc <vscale x 16 x i8> %in to <vscale x 16 x i1>
ret <vscale x 16 x i1> %out
}
define void @trunc_promoteIntRes(<vscale x 4 x i64> %0, i16* %ptr) {
; CHECK-LABEL: trunc_promoteIntRes:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1h { z0.s }, p0, [x0]
; CHECK-NEXT: ret
entry:
%1 = trunc <vscale x 4 x i64> %0 to <vscale x 4 x i16>
%2 = bitcast i16* %ptr to <vscale x 4 x i16>*
store <vscale x 4 x i16> %1, <vscale x 4 x i16>* %2, align 2
ret void
}