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[SLPVectorizer] Add initial alternate opcode support for cast instructions.
We currently only support binary instructions in the alternate opcode shuffles. This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism: 1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly. 2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this. 3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc. 4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements. Differential Revision: https://reviews.llvm.org/D49135 llvm-svn: 336804
This commit is contained in:
Simon Pilgrim
parent
594edf22ad
commit
17f835882b
@ -353,16 +353,22 @@ static InstructionsState getSameOpcode(ArrayRef<Value *> VL,
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if (llvm::any_of(VL, [](Value *V) { return !isa<Instruction>(V); }))
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return InstructionsState(VL[BaseIndex], nullptr, nullptr);
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bool IsCastOp = isa<CastInst>(VL[BaseIndex]);
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bool IsBinOp = isa<BinaryOperator>(VL[BaseIndex]);
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unsigned Opcode = cast<Instruction>(VL[BaseIndex])->getOpcode();
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unsigned AltOpcode = Opcode;
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unsigned AltIndex = BaseIndex;
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// Check for one alternate opcode from another BinaryOperator.
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// TODO - can we support other operators (casts etc.)?
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// TODO - generalize to support all operators (calls etc.).
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for (int Cnt = 0, E = VL.size(); Cnt < E; Cnt++) {
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unsigned InstOpcode = cast<Instruction>(VL[Cnt])->getOpcode();
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if (InstOpcode != Opcode && InstOpcode != AltOpcode) {
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if (Opcode == AltOpcode && IsCastOp && isa<CastInst>(VL[Cnt])) {
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AltOpcode = InstOpcode;
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AltIndex = Cnt;
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continue;
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}
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if (Opcode == AltOpcode && IsBinOp && isa<BinaryOperator>(VL[Cnt])) {
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AltOpcode = InstOpcode;
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AltIndex = Cnt;
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@ -2363,32 +2369,45 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
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return ReuseShuffleCost + VecCallCost - ScalarCallCost;
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}
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case Instruction::ShuffleVector: {
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assert(S.isAltShuffle() && Instruction::isBinaryOp(S.getOpcode()) &&
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Instruction::isBinaryOp(S.getAltOpcode()) &&
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assert(S.isAltShuffle() &&
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((Instruction::isBinaryOp(S.getOpcode()) &&
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Instruction::isBinaryOp(S.getAltOpcode())) ||
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(Instruction::isCast(S.getOpcode()) &&
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Instruction::isCast(S.getAltOpcode()))) &&
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"Invalid Shuffle Vector Operand");
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int ScalarCost = 0;
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if (NeedToShuffleReuses) {
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for (unsigned Idx : E->ReuseShuffleIndices) {
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Instruction *I = cast<Instruction>(VL[Idx]);
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ReuseShuffleCost -=
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TTI->getArithmeticInstrCost(I->getOpcode(), ScalarTy);
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ReuseShuffleCost -= TTI->getInstructionCost(
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I, TargetTransformInfo::TCK_RecipThroughput);
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}
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for (Value *V : VL) {
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Instruction *I = cast<Instruction>(V);
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ReuseShuffleCost +=
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TTI->getArithmeticInstrCost(I->getOpcode(), ScalarTy);
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ReuseShuffleCost += TTI->getInstructionCost(
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I, TargetTransformInfo::TCK_RecipThroughput);
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}
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}
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int VecCost = 0;
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for (Value *i : VL) {
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Instruction *I = cast<Instruction>(i);
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assert(S.isOpcodeOrAlt(I) && "Unexpected main/alternate opcode");
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ScalarCost += TTI->getArithmeticInstrCost(I->getOpcode(), ScalarTy);
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ScalarCost += TTI->getInstructionCost(
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I, TargetTransformInfo::TCK_RecipThroughput);
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}
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// VecCost is equal to sum of the cost of creating 2 vectors
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// and the cost of creating shuffle.
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VecCost = TTI->getArithmeticInstrCost(S.getOpcode(), VecTy);
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VecCost += TTI->getArithmeticInstrCost(S.getAltOpcode(), VecTy);
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if (Instruction::isBinaryOp(S.getOpcode())) {
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VecCost = TTI->getArithmeticInstrCost(S.getOpcode(), VecTy);
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VecCost += TTI->getArithmeticInstrCost(S.getAltOpcode(), VecTy);
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} else {
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Type *Src0SclTy = S.MainOp->getOperand(0)->getType();
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Type *Src1SclTy = S.AltOp->getOperand(0)->getType();
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VectorType *Src0Ty = VectorType::get(Src0SclTy, VL.size());
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VectorType *Src1Ty = VectorType::get(Src1SclTy, VL.size());
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VecCost = TTI->getCastInstrCost(S.getOpcode(), VecTy, Src0Ty);
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VecCost += TTI->getCastInstrCost(S.getAltOpcode(), VecTy, Src1Ty);
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}
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VecCost += TTI->getShuffleCost(TargetTransformInfo::SK_Select, VecTy, 0);
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return ReuseShuffleCost + VecCost - ScalarCost;
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}
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@ -3470,30 +3489,47 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) {
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}
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case Instruction::ShuffleVector: {
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ValueList LHSVL, RHSVL;
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assert(S.isAltShuffle() && Instruction::isBinaryOp(S.getOpcode()) &&
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Instruction::isBinaryOp(S.getAltOpcode()) &&
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assert(S.isAltShuffle() &&
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((Instruction::isBinaryOp(S.getOpcode()) &&
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Instruction::isBinaryOp(S.getAltOpcode())) ||
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(Instruction::isCast(S.getOpcode()) &&
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Instruction::isCast(S.getAltOpcode()))) &&
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"Invalid Shuffle Vector Operand");
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reorderAltShuffleOperands(S, E->Scalars, LHSVL, RHSVL);
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setInsertPointAfterBundle(E->Scalars, S);
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Value *LHS = vectorizeTree(LHSVL);
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Value *RHS = vectorizeTree(RHSVL);
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Value *LHS, *RHS;
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if (Instruction::isBinaryOp(S.getOpcode())) {
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reorderAltShuffleOperands(S, E->Scalars, LHSVL, RHSVL);
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setInsertPointAfterBundle(E->Scalars, S);
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LHS = vectorizeTree(LHSVL);
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RHS = vectorizeTree(RHSVL);
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} else {
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ValueList INVL;
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for (Value *V : E->Scalars)
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INVL.push_back(cast<Instruction>(V)->getOperand(0));
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setInsertPointAfterBundle(E->Scalars, S);
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LHS = vectorizeTree(INVL);
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}
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if (E->VectorizedValue) {
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LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
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return E->VectorizedValue;
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}
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// Create a vector of LHS op1 RHS
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Value *V0 = Builder.CreateBinOp(
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Value *V0, *V1;
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if (Instruction::isBinaryOp(S.getOpcode())) {
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V0 = Builder.CreateBinOp(
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static_cast<Instruction::BinaryOps>(S.getOpcode()), LHS, RHS);
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// Create a vector of LHS op2 RHS
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Value *V1 = Builder.CreateBinOp(
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V1 = Builder.CreateBinOp(
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static_cast<Instruction::BinaryOps>(S.getAltOpcode()), LHS, RHS);
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} else {
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V0 = Builder.CreateCast(
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static_cast<Instruction::CastOps>(S.getOpcode()), LHS, VecTy);
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V1 = Builder.CreateCast(
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static_cast<Instruction::CastOps>(S.getAltOpcode()), LHS, VecTy);
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}
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// Create shuffle to take alternate operations from the vector.
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// Also, gather up odd and even scalar ops to propagate IR flags to
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// Also, gather up main and alt scalar ops to propagate IR flags to
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// each vector operation.
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ValueList OpScalars, AltScalars;
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unsigned e = E->Scalars.size();
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@ -7,32 +7,71 @@
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; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512BW
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define <8 x float> @sitofp_uitofp(<8 x i32> %a) {
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; CHECK-LABEL: @sitofp_uitofp(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
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; CHECK-NEXT: [[A4:%.*]] = extractelement <8 x i32> [[A]], i32 4
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; CHECK-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
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; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
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; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
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; CHECK-NEXT: [[AB0:%.*]] = sitofp i32 [[A0]] to float
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; CHECK-NEXT: [[AB1:%.*]] = sitofp i32 [[A1]] to float
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; CHECK-NEXT: [[AB2:%.*]] = sitofp i32 [[A2]] to float
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; CHECK-NEXT: [[AB3:%.*]] = sitofp i32 [[A3]] to float
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; CHECK-NEXT: [[AB4:%.*]] = uitofp i32 [[A4]] to float
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; CHECK-NEXT: [[AB5:%.*]] = uitofp i32 [[A5]] to float
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; CHECK-NEXT: [[AB6:%.*]] = uitofp i32 [[A6]] to float
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; CHECK-NEXT: [[AB7:%.*]] = uitofp i32 [[A7]] to float
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; CHECK-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i32 0
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; CHECK-NEXT: [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
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; CHECK-NEXT: [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
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; CHECK-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
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; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
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; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
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; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
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; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
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; CHECK-NEXT: ret <8 x float> [[R7]]
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; SSE-LABEL: @sitofp_uitofp(
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; SSE-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
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; SSE-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
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; SSE-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
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; SSE-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
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; SSE-NEXT: [[A4:%.*]] = extractelement <8 x i32> [[A]], i32 4
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; SSE-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
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; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
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; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
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; SSE-NEXT: [[AB0:%.*]] = sitofp i32 [[A0]] to float
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; SSE-NEXT: [[AB1:%.*]] = sitofp i32 [[A1]] to float
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; SSE-NEXT: [[AB2:%.*]] = sitofp i32 [[A2]] to float
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; SSE-NEXT: [[AB3:%.*]] = sitofp i32 [[A3]] to float
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; SSE-NEXT: [[AB4:%.*]] = uitofp i32 [[A4]] to float
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; SSE-NEXT: [[AB5:%.*]] = uitofp i32 [[A5]] to float
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; SSE-NEXT: [[AB6:%.*]] = uitofp i32 [[A6]] to float
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; SSE-NEXT: [[AB7:%.*]] = uitofp i32 [[A7]] to float
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; SSE-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i32 0
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; SSE-NEXT: [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
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; SSE-NEXT: [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
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; SSE-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
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; SSE-NEXT: [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
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; SSE-NEXT: [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
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; SSE-NEXT: [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
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; SSE-NEXT: [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
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; SSE-NEXT: ret <8 x float> [[R7]]
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;
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; SLM-LABEL: @sitofp_uitofp(
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; SLM-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
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; SLM-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
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; SLM-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
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; SLM-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
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; SLM-NEXT: [[A4:%.*]] = extractelement <8 x i32> [[A]], i32 4
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; SLM-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
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; SLM-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
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; SLM-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
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; SLM-NEXT: [[AB0:%.*]] = sitofp i32 [[A0]] to float
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; SLM-NEXT: [[AB1:%.*]] = sitofp i32 [[A1]] to float
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; SLM-NEXT: [[AB2:%.*]] = sitofp i32 [[A2]] to float
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; SLM-NEXT: [[AB3:%.*]] = sitofp i32 [[A3]] to float
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; SLM-NEXT: [[AB4:%.*]] = uitofp i32 [[A4]] to float
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; SLM-NEXT: [[AB5:%.*]] = uitofp i32 [[A5]] to float
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; SLM-NEXT: [[AB6:%.*]] = uitofp i32 [[A6]] to float
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; SLM-NEXT: [[AB7:%.*]] = uitofp i32 [[A7]] to float
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; SLM-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i32 0
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; SLM-NEXT: [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
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; SLM-NEXT: [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
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; SLM-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
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; SLM-NEXT: [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
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; SLM-NEXT: [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
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; SLM-NEXT: [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
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; SLM-NEXT: [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
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; SLM-NEXT: ret <8 x float> [[R7]]
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;
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; AVX-LABEL: @sitofp_uitofp(
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; AVX-NEXT: [[TMP1:%.*]] = sitofp <8 x i32> [[A:%.*]] to <8 x float>
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; AVX-NEXT: [[TMP2:%.*]] = uitofp <8 x i32> [[A]] to <8 x float>
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; AVX-NEXT: [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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; AVX-NEXT: ret <8 x float> [[R7]]
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;
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; AVX512-LABEL: @sitofp_uitofp(
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; AVX512-NEXT: [[TMP1:%.*]] = sitofp <8 x i32> [[A:%.*]] to <8 x float>
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; AVX512-NEXT: [[TMP2:%.*]] = uitofp <8 x i32> [[A]] to <8 x float>
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; AVX512-NEXT: [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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; AVX512-NEXT: ret <8 x float> [[R7]]
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;
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%a0 = extractelement <8 x i32> %a, i32 0
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%a1 = extractelement <8 x i32> %a, i32 1
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@ -62,32 +101,92 @@ define <8 x float> @sitofp_uitofp(<8 x i32> %a) {
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}
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define <8 x i32> @fptosi_fptoui(<8 x float> %a) {
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; CHECK-LABEL: @fptosi_fptoui(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
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; CHECK-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
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; CHECK-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
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; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
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; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
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; CHECK-NEXT: [[AB0:%.*]] = fptosi float [[A0]] to i32
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; CHECK-NEXT: [[AB1:%.*]] = fptosi float [[A1]] to i32
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; CHECK-NEXT: [[AB2:%.*]] = fptosi float [[A2]] to i32
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; CHECK-NEXT: [[AB3:%.*]] = fptosi float [[A3]] to i32
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; CHECK-NEXT: [[AB4:%.*]] = fptoui float [[A4]] to i32
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; CHECK-NEXT: [[AB5:%.*]] = fptoui float [[A5]] to i32
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; CHECK-NEXT: [[AB6:%.*]] = fptoui float [[A6]] to i32
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; CHECK-NEXT: [[AB7:%.*]] = fptoui float [[A7]] to i32
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; CHECK-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
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; CHECK-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
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; CHECK-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
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; CHECK-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
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; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
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; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
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; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
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; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
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; CHECK-NEXT: ret <8 x i32> [[R7]]
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; SSE-LABEL: @fptosi_fptoui(
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; SSE-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
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; SSE-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
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; SSE-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
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; SSE-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
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; SSE-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
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; SSE-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
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; SSE-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
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; SSE-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
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; SSE-NEXT: [[AB0:%.*]] = fptosi float [[A0]] to i32
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; SSE-NEXT: [[AB1:%.*]] = fptosi float [[A1]] to i32
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; SSE-NEXT: [[AB2:%.*]] = fptosi float [[A2]] to i32
|
||||
; SSE-NEXT: [[AB3:%.*]] = fptosi float [[A3]] to i32
|
||||
; SSE-NEXT: [[AB4:%.*]] = fptoui float [[A4]] to i32
|
||||
; SSE-NEXT: [[AB5:%.*]] = fptoui float [[A5]] to i32
|
||||
; SSE-NEXT: [[AB6:%.*]] = fptoui float [[A6]] to i32
|
||||
; SSE-NEXT: [[AB7:%.*]] = fptoui float [[A7]] to i32
|
||||
; SSE-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
|
||||
; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
|
||||
; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
|
||||
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
|
||||
; SSE-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
|
||||
; SSE-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
|
||||
; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
|
||||
; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
|
||||
; SSE-NEXT: ret <8 x i32> [[R7]]
|
||||
;
|
||||
; SLM-LABEL: @fptosi_fptoui(
|
||||
; SLM-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
|
||||
; SLM-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
|
||||
; SLM-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
|
||||
; SLM-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
|
||||
; SLM-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
|
||||
; SLM-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
|
||||
; SLM-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
|
||||
; SLM-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
|
||||
; SLM-NEXT: [[AB0:%.*]] = fptosi float [[A0]] to i32
|
||||
; SLM-NEXT: [[AB1:%.*]] = fptosi float [[A1]] to i32
|
||||
; SLM-NEXT: [[AB2:%.*]] = fptosi float [[A2]] to i32
|
||||
; SLM-NEXT: [[AB3:%.*]] = fptosi float [[A3]] to i32
|
||||
; SLM-NEXT: [[AB4:%.*]] = fptoui float [[A4]] to i32
|
||||
; SLM-NEXT: [[AB5:%.*]] = fptoui float [[A5]] to i32
|
||||
; SLM-NEXT: [[AB6:%.*]] = fptoui float [[A6]] to i32
|
||||
; SLM-NEXT: [[AB7:%.*]] = fptoui float [[A7]] to i32
|
||||
; SLM-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
|
||||
; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
|
||||
; SLM-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
|
||||
; SLM-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
|
||||
; SLM-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
|
||||
; SLM-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
|
||||
; SLM-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
|
||||
; SLM-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
|
||||
; SLM-NEXT: ret <8 x i32> [[R7]]
|
||||
;
|
||||
; AVX-LABEL: @fptosi_fptoui(
|
||||
; AVX-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
|
||||
; AVX-NEXT: [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
|
||||
; AVX-NEXT: [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
|
||||
; AVX-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
|
||||
; AVX-NEXT: [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
|
||||
; AVX-NEXT: [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
|
||||
; AVX-NEXT: [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
|
||||
; AVX-NEXT: [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
|
||||
; AVX-NEXT: [[AB0:%.*]] = fptosi float [[A0]] to i32
|
||||
; AVX-NEXT: [[AB1:%.*]] = fptosi float [[A1]] to i32
|
||||
; AVX-NEXT: [[AB2:%.*]] = fptosi float [[A2]] to i32
|
||||
; AVX-NEXT: [[AB3:%.*]] = fptosi float [[A3]] to i32
|
||||
; AVX-NEXT: [[AB4:%.*]] = fptoui float [[A4]] to i32
|
||||
; AVX-NEXT: [[AB5:%.*]] = fptoui float [[A5]] to i32
|
||||
; AVX-NEXT: [[AB6:%.*]] = fptoui float [[A6]] to i32
|
||||
; AVX-NEXT: [[AB7:%.*]] = fptoui float [[A7]] to i32
|
||||
; AVX-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
|
||||
; AVX-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
|
||||
; AVX-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
|
||||
; AVX-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
|
||||
; AVX-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
|
||||
; AVX-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
|
||||
; AVX-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
|
||||
; AVX-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
|
||||
; AVX-NEXT: ret <8 x i32> [[R7]]
|
||||
;
|
||||
; AVX512-LABEL: @fptosi_fptoui(
|
||||
; AVX512-NEXT: [[TMP1:%.*]] = fptosi <8 x float> [[A:%.*]] to <8 x i32>
|
||||
; AVX512-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[A]] to <8 x i32>
|
||||
; AVX512-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
|
||||
; AVX512-NEXT: ret <8 x i32> [[R7]]
|
||||
;
|
||||
%a0 = extractelement <8 x float> %a, i32 0
|
||||
%a1 = extractelement <8 x float> %a, i32 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user