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This is the real fix for the previous register allocator problem.

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Physical registers should not float around.

llvm-svn: 7587
This commit is contained in:
Chris Lattner 2003-08-05 00:48:47 +00:00
parent 3b098f3fdd
commit 17fc21b5fa
3 changed files with 4 additions and 1 deletions
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2
lib/Target/X86/InstSelectSimple.cpp
View File

@ -646,6 +646,8 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
BuildMI(BB, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::BH);
BuildMI(BB, X86::IMPLICIT_DEF, 0, X86::AH);
BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
// NOTE: visitSetCondInst knows that the value is dumped into the BL
// register at this point for long values...

2
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -470,7 +470,7 @@ void Emitter::emitInstruction(MachineInstr &MI) {
switch (Desc.TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
if (Opcode != X86::IMPLICIT_USE)
if (Opcode != X86::IMPLICIT_USE && Opcode != X86::IMPLICIT_DEF)
std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI;
break;

1
lib/Target/X86/X86InstrInfo.td
View File

@ -107,6 +107,7 @@ def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...