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https://github.com/RPCS3/llvm-mirror.git
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Bug fixes:
(1) Ensure that delay slot instructions are not moved out of place (this
was happening for some CALL instructions). Basically, we need to
move all delay slot instructions out of the graph and handle them
along with the delayed control transfer instruction.
(2) Mark scheduled instructions correctly when instructions are scheduled
in more than one cycle in a single step (due to delay slots).
llvm-svn: 678
This commit is contained in:
Vikram S. Adve
parent
d376407048
commit
180dee14b8
@ -9,16 +9,26 @@
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// 7/23/01 - Vikram Adve - Created
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//**************************************************************************/
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//************************* User Include Files *****************************/
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "SchedPriorities.h"
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#include "llvm/Analysis/LiveVar/BBLiveVar.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Instruction.h"
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//************************ System Include Files *****************************/
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#include <hash_set>
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#include <algorithm>
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#include <iterator>
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//************************* External Data Types *****************************/
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cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
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"enable instruction scheduling debugging information",
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clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
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@ -27,55 +37,12 @@ cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
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clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
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//************************* Internal Data Types *****************************/
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class InstrSchedule;
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class SchedulingManager;
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class DelaySlotInfo;
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static void ForwardListSchedule (SchedulingManager& S);
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static void RecordSchedule (const BasicBlock* bb,
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const SchedulingManager& S);
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static unsigned ChooseOneGroup (SchedulingManager& S);
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static void MarkSuccessorsReady (SchedulingManager& S,
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const SchedGraphNode* node);
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static unsigned FindSlotChoices (SchedulingManager& S,
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DelaySlotInfo*& getDelaySlotInfo);
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static void AssignInstructionsToSlots(class SchedulingManager& S,
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unsigned maxIssue);
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static void ScheduleInstr (class SchedulingManager& S,
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const SchedGraphNode* node,
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unsigned int slotNum,
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cycles_t curTime);
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static bool ViolatesMinimumGap (const SchedulingManager& S,
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MachineOpCode opCode,
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const cycles_t inCycle);
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static bool ConflictsWithChoices (const SchedulingManager& S,
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MachineOpCode opCode);
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static void ChooseInstructionsForDelaySlots(SchedulingManager& S,
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const BasicBlock* bb,
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SchedGraph* graph);
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static bool NodeCanFillDelaySlot (const SchedulingManager& S,
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const SchedGraphNode* node,
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const SchedGraphNode* brNode,
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bool nodeIsPredecessor);
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static void MarkNodeForDelaySlot (SchedulingManager& S,
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SchedGraph* graph,
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SchedGraphNode* node,
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const SchedGraphNode* brNode,
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bool nodeIsPredecessor);
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//************************* Internal Data Types *****************************/
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//----------------------------------------------------------------------
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// class InstrGroup:
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@ -369,7 +336,7 @@ public:
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delayedNodeSlotNum = slotNum;
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}
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void scheduleDelayedNode (SchedulingManager& S);
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unsigned scheduleDelayedNode (SchedulingManager& S);
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};
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@ -539,7 +506,7 @@ public:
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if (createIfMissing)
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{
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dinfo = new DelaySlotInfo(bn,
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getInstrInfo().getNumDelaySlots(bn->getMachineInstr()->getOpCode()));
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getInstrInfo().getNumDelaySlots(bn->getMachineInstr()->getOpCode()));
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delaySlotInfoForBranches[bn] = dinfo;
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}
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else
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@ -608,159 +575,63 @@ SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
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}
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}
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//************************* External Functions *****************************/
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructionsWithSSA
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//
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// Purpose:
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// Entry point for instruction scheduling on SSA form.
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// Schedules the machine instructions generated by instruction selection.
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// Assumes that register allocation has not been done, i.e., operands
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// are still in SSA form.
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//---------------------------------------------------------------------------
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bool
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ScheduleInstructionsWithSSA(Method* method,
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const TargetMachine &target)
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{
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SchedGraphSet graphSet(method, target);
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if (SchedDebugLevel >= Sched_PrintSchedGraphs)
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{
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cout << endl << "*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING"
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<< endl;
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graphSet.dump();
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}
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for (SchedGraphSet::const_iterator GI=graphSet.begin();
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GI != graphSet.end(); ++GI)
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{
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SchedGraph* graph = (*GI).second;
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const vector<const BasicBlock*>& bbvec = graph->getBasicBlocks();
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assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
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const BasicBlock* bb = bbvec[0];
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
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SchedPriorities schedPrio(method, graph); // expensive!
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SchedulingManager S(target, graph, schedPrio);
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ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
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ForwardListSchedule(S); // computes schedule in S
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RecordSchedule((*GI).first, S); // records schedule in BB
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}
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if (SchedDebugLevel >= Sched_PrintMachineCode)
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{
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cout << endl
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<< "*** Machine instructions after INSTRUCTION SCHEDULING" << endl;
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PrintMachineInstructions(method);
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}
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return false; // no reason to fail yet
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}
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// Check minimum gap requirements relative to instructions scheduled in
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// previous cycles.
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// Note that we do not need to consider `nextEarliestIssueTime' here because
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// that is also captured in the earliest start times for each opcode.
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//
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static inline bool
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ViolatesMinimumGap(const SchedulingManager& S,
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MachineOpCode opCode,
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const cycles_t inCycle)
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{
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return (inCycle < S.getEarliestStartTimeForOp(opCode));
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}
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// Check if the instruction would conflict with instructions already
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// chosen for the current cycle
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//
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static inline bool
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ConflictsWithChoices(const SchedulingManager& S,
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MachineOpCode opCode)
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{
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// Check if the instruction must issue by itself, and some feasible
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// choices have already been made for this cycle
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if (S.getNumChoices() > 0 && S.schedInfo.isSingleIssue(opCode))
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return true;
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// For each class that opCode belongs to, check if there are too many
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// instructions of that class.
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//
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const InstrSchedClass sc = S.schedInfo.getSchedClass(opCode);
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return (S.getNumChoicesInClass(sc) == S.schedInfo.getMaxIssueForClass(sc));
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}
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// Check if any issue restrictions would prevent the instruction from
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// being issued in the current cycle
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//
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bool
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instrIsFeasible(const SchedulingManager& S,
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MachineOpCode opCode)
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{
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// skip the instruction if it cannot be issued due to issue restrictions
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// caused by previously issued instructions
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if (ViolatesMinimumGap(S, opCode, S.getTime()))
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return false;
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// skip the instruction if it cannot be issued due to issue restrictions
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// caused by previously chosen instructions for the current cycle
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if (ConflictsWithChoices(S, opCode))
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return false;
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return true;
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}
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//************************* Internal Functions *****************************/
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static void
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ForwardListSchedule(SchedulingManager& S)
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AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
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{
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unsigned N;
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const SchedGraphNode* node;
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// find the slot to start from, in the current cycle
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unsigned int startSlot = 0;
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cycles_t curTime = S.getTime();
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S.schedPrio.initialize();
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assert(maxIssue > 0 && maxIssue <= S.nslots - startSlot);
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while ((N = S.schedPrio.getNumReady()) > 0)
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// If only one instruction can be issued, do so.
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if (maxIssue == 1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if (S.getChoicesForSlot(s).size() > 0)
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{// found the one instruction
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S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
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return;
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}
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// Otherwise, choose from the choices for each slot
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//
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InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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assert(igroup != NULL && "Group creation failed?");
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// Find a slot that has only a single choice, and take it.
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// If all slots have 0 or multiple choices, pick the first slot with
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// choices and use its last instruction (just to avoid shifting the vector).
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unsigned numIssued;
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for (numIssued = 0; numIssued < maxIssue; numIssued++)
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{
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// Choose one group of instructions for a cycle. This will
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// advance S.getTime() to the first cycle instructions can be issued.
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// It may also schedule delay slot instructions in later cycles,
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// but those are ignored here because they are outside the graph.
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//
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unsigned numIssued = ChooseOneGroup(S);
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assert(numIssued > 0 && "Deadlock in list scheduling algorithm?");
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// Notify the priority manager of scheduled instructions and mark
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// any successors that may now be ready
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//
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const InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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for (unsigned int s=0; s < S.nslots; s++)
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if ((node = (*igroup)[s]) != NULL)
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int chosenSlot = -1, chosenNodeIndex = -1;
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1)
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{
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S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
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MarkSuccessorsReady(S, node);
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chosenSlot = (int) s;
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break;
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}
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// Move to the next the next earliest cycle for which
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// an instruction can be issued, or the next earliest in which
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// one will be ready, or to the next cycle, whichever is latest.
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//
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S.updateTime(max(S.getTime() + 1,
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max(S.getEarliestIssueTime(),
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S.schedPrio.getEarliestReadyTime())));
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if (chosenSlot == -1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0)
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{
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chosenSlot = (int) s;
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break;
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}
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if (chosenSlot != -1)
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{ // Insert the chosen instr in the chosen slot and
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// erase it from all slots.
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const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
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S.scheduleInstr(node, chosenSlot, curTime);
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}
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}
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assert(numIssued > 0 && "Should not happen when maxIssue > 0!");
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}
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@ -809,46 +680,6 @@ RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
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}
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static unsigned
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ChooseOneGroup(SchedulingManager& S)
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{
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assert(S.schedPrio.getNumReady() > 0
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&& "Don't get here without ready instructions.");
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DelaySlotInfo* getDelaySlotInfo = NULL;
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// Choose up to `nslots' feasible instructions and their possible slots.
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unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
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while (numIssued == 0)
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{
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S.updateTime(S.getTime()+1);
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numIssued = FindSlotChoices(S, getDelaySlotInfo);
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}
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AssignInstructionsToSlots(S, numIssued);
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if (getDelaySlotInfo != NULL)
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getDelaySlotInfo->scheduleDelayedNode(S);
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// Print trace of scheduled instructions before newly ready ones
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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{
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cout << " Cycle " << S.getTime() << " : Scheduled instructions:\n";
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const InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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for (unsigned int s=0; s < S.nslots; s++)
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{
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cout << " ";
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if ((*igroup)[s] != NULL)
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cout << * ((*igroup)[s])->getMachineInstr() << endl;
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else
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cout << "<none>" << endl;
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}
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}
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return numIssued;
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}
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static void
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MarkSuccessorsReady(SchedulingManager& S, const SchedGraphNode* node)
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@ -1025,7 +856,7 @@ FindSlotChoices(SchedulingManager& S,
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{
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// Try to assign every other instruction to a lower numbered
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// slot than delayedNodeSlot.
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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MachineOpCode opCode =S.getChoice(i)->getMachineInstr()->getOpCode();
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bool noSlotFound = true;
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unsigned int s;
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for (s=startSlot; s < delayedNodeSlot; s++)
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@ -1093,7 +924,7 @@ FindSlotChoices(SchedulingManager& S,
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for (unsigned i=0;
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i < S.getNumChoices() && i < indexForBreakingNode; i++)
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{
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MachineOpCode opCode = S.getChoice(i)->getMachineInstr()->getOpCode();
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MachineOpCode opCode =S.getChoice(i)->getMachineInstr()->getOpCode();
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// If a higher priority instruction cannot be assigned to
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// any earlier slots, don't schedule the breaking instruction.
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@ -1144,63 +975,95 @@ FindSlotChoices(SchedulingManager& S,
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}
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static void
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AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
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static unsigned
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ChooseOneGroup(SchedulingManager& S)
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{
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// find the slot to start from, in the current cycle
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unsigned int startSlot = 0;
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cycles_t curTime = S.getTime();
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assert(S.schedPrio.getNumReady() > 0
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&& "Don't get here without ready instructions.");
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assert(maxIssue > 0 && maxIssue <= S.nslots - startSlot);
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cycles_t firstCycle = S.getTime();
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DelaySlotInfo* getDelaySlotInfo = NULL;
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// If only one instruction can be issued, do so.
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if (maxIssue == 1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if (S.getChoicesForSlot(s).size() > 0)
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{// found the one instruction
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S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
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return;
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}
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// Choose up to `nslots' feasible instructions and their possible slots.
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unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
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// Otherwise, choose from the choices for each slot
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//
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InstrGroup* igroup = S.isched.getIGroup(S.getTime());
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assert(igroup != NULL && "Group creation failed?");
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// Find a slot that has only a single choice, and take it.
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// If all slots have 0 or multiple choices, pick the first slot with
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// choices and use its last instruction (just to avoid shifting the vector).
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unsigned numIssued;
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for (numIssued = 0; numIssued < maxIssue; numIssued++)
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while (numIssued == 0)
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{
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int chosenSlot = -1, chosenNodeIndex = -1;
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1)
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{
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chosenSlot = (int) s;
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break;
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}
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if (chosenSlot == -1)
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for (unsigned s=startSlot; s < S.nslots; s++)
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if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0)
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{
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chosenSlot = (int) s;
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break;
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}
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if (chosenSlot != -1)
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{ // Insert the chosen instr in the chosen slot and
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// erase it from all slots.
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const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
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S.scheduleInstr(node, chosenSlot, curTime);
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}
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S.updateTime(S.getTime()+1);
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numIssued = FindSlotChoices(S, getDelaySlotInfo);
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}
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assert(numIssued > 0 && "Should not happen when maxIssue > 0!");
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AssignInstructionsToSlots(S, numIssued);
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if (getDelaySlotInfo != NULL)
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numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
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// Print trace of scheduled instructions before newly ready ones
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if (SchedDebugLevel >= Sched_PrintSchedTrace)
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{
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for (cycles_t c = firstCycle; c <= S.getTime(); c++)
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{
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cout << " Cycle " << c << " : Scheduled instructions:\n";
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const InstrGroup* igroup = S.isched.getIGroup(c);
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for (unsigned int s=0; s < S.nslots; s++)
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{
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cout << " ";
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if ((*igroup)[s] != NULL)
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cout << * ((*igroup)[s])->getMachineInstr() << endl;
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else
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cout << "<none>" << endl;
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}
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}
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}
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return numIssued;
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}
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static void
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ForwardListSchedule(SchedulingManager& S)
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{
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unsigned N;
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const SchedGraphNode* node;
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S.schedPrio.initialize();
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while ((N = S.schedPrio.getNumReady()) > 0)
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{
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cycles_t nextCycle = S.getTime();
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// Choose one group of instructions for a cycle, plus any delay slot
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// instructions (which may overflow into successive cycles).
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// This will advance S.getTime() to the last cycle in which
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// instructions are actually issued.
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//
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unsigned numIssued = ChooseOneGroup(S);
|
||||
assert(numIssued > 0 && "Deadlock in list scheduling algorithm?");
|
||||
|
||||
// Notify the priority manager of scheduled instructions and mark
|
||||
// any successors that may now be ready
|
||||
//
|
||||
for (cycles_t c = nextCycle; c <= S.getTime(); c++)
|
||||
{
|
||||
const InstrGroup* igroup = S.isched.getIGroup(c);
|
||||
for (unsigned int s=0; s < S.nslots; s++)
|
||||
if ((node = (*igroup)[s]) != NULL)
|
||||
{
|
||||
S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
|
||||
MarkSuccessorsReady(S, node);
|
||||
}
|
||||
}
|
||||
|
||||
// Move to the next the next earliest cycle for which
|
||||
// an instruction can be issued, or the next earliest in which
|
||||
// one will be ready, or to the next cycle, whichever is latest.
|
||||
//
|
||||
S.updateTime(max(S.getTime() + 1,
|
||||
max(S.getEarliestIssueTime(),
|
||||
S.schedPrio.getEarliestReadyTime())));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Code for filling delay slots for delayed terminator instructions
|
||||
@ -1211,107 +1074,7 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
|
||||
// when we cannot find single-cycle instructions that can be reordered.
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
static void
|
||||
ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
const BasicBlock* bb,
|
||||
SchedGraph* graph)
|
||||
{
|
||||
// Look for instructions that can be used for delay slots.
|
||||
// Remove them from the graph, and mark them to be used for delay slots.
|
||||
const MachineInstrInfo& mii = S.getInstrInfo();
|
||||
const TerminatorInst* term = bb->getTerminator();
|
||||
MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
|
||||
|
||||
// Find the first branch instr in the sequence of machine instrs for term
|
||||
//
|
||||
unsigned first = 0;
|
||||
while (! mii.isBranch(termMvec[first]->getOpCode()))
|
||||
++first;
|
||||
assert(first < termMvec.size() &&
|
||||
"No branch instructions for BR? Ok, but weird! Delete assertion.");
|
||||
if (first == termMvec.size())
|
||||
return;
|
||||
|
||||
SchedGraphNode* brNode = graph->getGraphNodeForInstr(termMvec[first]);
|
||||
assert(! mii.isCall(brNode->getMachineInstr()->getOpCode()) && "Call used as terminator?");
|
||||
|
||||
unsigned ndelays = mii.getNumDelaySlots(brNode->getMachineInstr()->getOpCode());
|
||||
if (ndelays == 0)
|
||||
return;
|
||||
|
||||
// Use vectors to remember the nodes chosen for delay slots, and the
|
||||
// NOPs that will be unused. We cannot remove them from the graph while
|
||||
// walking through the preds and succs of the brNode here, so we
|
||||
// remember the nodes in the vectors and remove them later.
|
||||
// We use separate vectors for the single-cycle and multi-cycle nodes,
|
||||
// so that we can give preference to single-cycle nodes.
|
||||
//
|
||||
vector<SchedGraphNode*> sdelayNodeVec;
|
||||
vector<SchedGraphNode*> mdelayNodeVec;
|
||||
vector<SchedGraphNode*> nopNodeVec;
|
||||
unsigned numUseful = 0;
|
||||
|
||||
sdelayNodeVec.reserve(ndelays);
|
||||
|
||||
for (sg_pred_iterator P = pred_begin(brNode);
|
||||
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
|
||||
if (! (*P)->isDummyNode() &&
|
||||
! mii.isNop((*P)->getMachineInstr()->getOpCode()) &&
|
||||
NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
|
||||
{
|
||||
++numUseful;
|
||||
if (mii.maxLatency((*P)->getMachineInstr()->getOpCode()) > 1)
|
||||
mdelayNodeVec.push_back(*P);
|
||||
else
|
||||
sdelayNodeVec.push_back(*P);
|
||||
}
|
||||
|
||||
// If not enough single-cycle instructions were found, select the
|
||||
// lowest-latency multi-cycle instructions and use them.
|
||||
// Note that this is the most efficient code when only 1 (or even 2)
|
||||
// values need to be selected.
|
||||
//
|
||||
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
|
||||
{
|
||||
unsigned latency;
|
||||
unsigned minLatency = mii.maxLatency(mdelayNodeVec[0]->getMachineInstr()->getOpCode());
|
||||
unsigned minIndex = 0;
|
||||
for (unsigned i=1; i < mdelayNodeVec.size(); i++)
|
||||
if (minLatency >=
|
||||
(latency = mii.maxLatency(mdelayNodeVec[i]->getMachineInstr()->getOpCode())))
|
||||
{
|
||||
minLatency = latency;
|
||||
minIndex = i;
|
||||
}
|
||||
sdelayNodeVec.push_back(mdelayNodeVec[minIndex]);
|
||||
if (sdelayNodeVec.size() < ndelays) // avoid the last erase!
|
||||
mdelayNodeVec.erase(mdelayNodeVec.begin() + minIndex);
|
||||
}
|
||||
|
||||
// Now, remove the NOPs currently in delay slots from the graph.
|
||||
// If not enough useful instructions were found, use the NOPs to
|
||||
// fill delay slots, otherwise, just discard them.
|
||||
for (sg_succ_iterator I=succ_begin(brNode); I != succ_end(brNode); ++I)
|
||||
if (! (*I)->isDummyNode()
|
||||
&& mii.isNop((*I)->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
if (sdelayNodeVec.size() < ndelays)
|
||||
sdelayNodeVec.push_back(*I);
|
||||
else
|
||||
nopNodeVec.push_back(*I);
|
||||
}
|
||||
|
||||
// Mark the nodes chosen for delay slots. This removes them from the graph.
|
||||
for (unsigned i=0; i < sdelayNodeVec.size(); i++)
|
||||
MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], brNode, true);
|
||||
|
||||
// And remove the unused NOPs from the graph.
|
||||
for (unsigned i=0; i < nopNodeVec.size(); i++)
|
||||
graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
static bool
|
||||
NodeCanFillDelaySlot(const SchedulingManager& S,
|
||||
const SchedGraphNode* node,
|
||||
const SchedGraphNode* brNode,
|
||||
@ -1367,7 +1130,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
static void
|
||||
MarkNodeForDelaySlot(SchedulingManager& S,
|
||||
SchedGraph* graph,
|
||||
SchedGraphNode* node,
|
||||
@ -1391,10 +1154,173 @@ MarkNodeForDelaySlot(SchedulingManager& S,
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
|
||||
SchedGraphNode* brNode,
|
||||
vector<SchedGraphNode*>& sdelayNodeVec)
|
||||
{
|
||||
const MachineInstrInfo& mii = S.getInstrInfo();
|
||||
unsigned ndelays =
|
||||
mii.getNumDelaySlots(brNode->getMachineInstr()->getOpCode());
|
||||
|
||||
if (ndelays == 0)
|
||||
return;
|
||||
|
||||
sdelayNodeVec.reserve(ndelays);
|
||||
|
||||
// Use a separate vector to hold the feasible multi-cycle nodes.
|
||||
// These will be used if not enough single-cycle nodes are found.
|
||||
//
|
||||
vector<SchedGraphNode*> mdelayNodeVec;
|
||||
|
||||
for (sg_pred_iterator P = pred_begin(brNode);
|
||||
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
|
||||
if (! (*P)->isDummyNode() &&
|
||||
! mii.isNop((*P)->getMachineInstr()->getOpCode()) &&
|
||||
NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
|
||||
{
|
||||
if (mii.maxLatency((*P)->getMachineInstr()->getOpCode()) > 1)
|
||||
mdelayNodeVec.push_back(*P);
|
||||
else
|
||||
sdelayNodeVec.push_back(*P);
|
||||
}
|
||||
|
||||
// If not enough single-cycle instructions were found, select the
|
||||
// lowest-latency multi-cycle instructions and use them.
|
||||
// Note that this is the most efficient code when only 1 (or even 2)
|
||||
// values need to be selected.
|
||||
//
|
||||
while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
|
||||
{
|
||||
unsigned lmin =
|
||||
mii.maxLatency(mdelayNodeVec[0]->getMachineInstr()->getOpCode());
|
||||
unsigned minIndex = 0;
|
||||
for (unsigned i=1; i < mdelayNodeVec.size(); i++)
|
||||
{
|
||||
unsigned li =
|
||||
mii.maxLatency(mdelayNodeVec[i]->getMachineInstr()->getOpCode());
|
||||
if (lmin >= li)
|
||||
{
|
||||
lmin = li;
|
||||
minIndex = i;
|
||||
}
|
||||
}
|
||||
sdelayNodeVec.push_back(mdelayNodeVec[minIndex]);
|
||||
if (sdelayNodeVec.size() < ndelays) // avoid the last erase!
|
||||
mdelayNodeVec.erase(mdelayNodeVec.begin() + minIndex);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Remove the NOPs currently in delay slots from the graph.
|
||||
// Mark instructions specified in sdelayNodeVec to replace them.
|
||||
// If not enough useful instructions were found, mark the NOPs to be used
|
||||
// for filling delay slots, otherwise, otherwise just discard them.
|
||||
//
|
||||
void
|
||||
ReplaceNopsWithUsefulInstr(SchedulingManager& S,
|
||||
SchedGraphNode* node,
|
||||
vector<SchedGraphNode*> sdelayNodeVec,
|
||||
SchedGraph* graph)
|
||||
{
|
||||
vector<SchedGraphNode*> nopNodeVec;
|
||||
const MachineInstrInfo& mii = S.getInstrInfo();
|
||||
unsigned ndelays= mii.getNumDelaySlots(node->getMachineInstr()->getOpCode());
|
||||
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
|
||||
|
||||
// Remove the NOPs currently in delay slots from the graph.
|
||||
// If not enough useful instructions were found, use the NOPs to
|
||||
// fill delay slots, otherwise, just discard them.
|
||||
for (sg_succ_iterator I=succ_begin(node); I != succ_end(node); ++I)
|
||||
if (! (*I)->isDummyNode()
|
||||
&& mii.isNop((*I)->getMachineInstr()->getOpCode()))
|
||||
{
|
||||
if (sdelayNodeVec.size() < ndelays)
|
||||
sdelayNodeVec.push_back(*I);
|
||||
else
|
||||
nopNodeVec.push_back(*I);
|
||||
}
|
||||
assert(sdelayNodeVec.size() == ndelays);
|
||||
|
||||
// Mark the nodes chosen for delay slots. This removes them from the graph.
|
||||
for (unsigned i=0; i < sdelayNodeVec.size(); i++)
|
||||
MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], node, true);
|
||||
|
||||
// And remove the unused NOPs from the graph.
|
||||
for (unsigned i=0; i < nopNodeVec.size(); i++)
|
||||
graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
|
||||
}
|
||||
|
||||
|
||||
// For all delayed instructions, choose instructions to put in the delay
|
||||
// slots and pull those out of the graph. Mark them for the delay slots
|
||||
// in the DelaySlotInfo object for that graph node. If no useful work
|
||||
// is found for a delay slot, use the NOP that is currently in that slot.
|
||||
//
|
||||
// We try to fill the delay slots with useful work for all instructions
|
||||
// except CALLs. For CALLs, it is nearly always possible to use one of the
|
||||
// call sequence instrs and putting anything else in the delay slot could be
|
||||
// suboptimal.
|
||||
//
|
||||
static void
|
||||
ChooseInstructionsForDelaySlots(SchedulingManager& S,
|
||||
const BasicBlock* bb,
|
||||
SchedGraph* graph)
|
||||
{
|
||||
const MachineInstrInfo& mii = S.getInstrInfo();
|
||||
const TerminatorInst* termInstr = bb->getTerminator();
|
||||
MachineCodeForVMInstr& termMvec = termInstr->getMachineInstrVec();
|
||||
vector<SchedGraphNode*> delayNodeVec;
|
||||
const MachineInstr* brInstr;
|
||||
|
||||
assert(termInstr->getOpcode() != Instruction::Call
|
||||
&& "Call used as terminator?");
|
||||
|
||||
// To find instructions that need delay slots without searching the entire
|
||||
// machine code, we assume the only delayed instructions are CALLs or
|
||||
// instructions generated for the terminator inst.
|
||||
// Find the first branch instr in the sequence of machine instrs for term
|
||||
//
|
||||
unsigned first = 0;
|
||||
while (first < termMvec.size() &&
|
||||
! mii.isBranch(termMvec[first]->getOpCode()))
|
||||
{
|
||||
++first;
|
||||
}
|
||||
assert(first < termMvec.size() &&
|
||||
"No branch instructions for BR? Ok, but weird! Delete assertion.");
|
||||
|
||||
brInstr = (first < termMvec.size())? termMvec[first] : NULL;
|
||||
|
||||
// Compute a vector of the nodes chosen for delay slots and then
|
||||
// mark delay slots to replace NOPs with these useful instructions.
|
||||
//
|
||||
if (brInstr != NULL)
|
||||
{
|
||||
SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
|
||||
FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
|
||||
ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
|
||||
}
|
||||
|
||||
// Also mark delay slots for other delayed instructions to hold NOPs.
|
||||
// Simply passing in an empty delayNodeVec will have this effect.
|
||||
//
|
||||
delayNodeVec.clear();
|
||||
const MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
|
||||
for (unsigned i=0; i < bbMvec.size(); i++)
|
||||
if (bbMvec[i] != brInstr &&
|
||||
mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
|
||||
{
|
||||
SchedGraphNode* node = graph->getGraphNodeForInstr(bbMvec[i]);
|
||||
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Schedule the delayed branch and its delay slots
|
||||
//
|
||||
void
|
||||
unsigned
|
||||
DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
{
|
||||
assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch");
|
||||
@ -1461,5 +1387,130 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
|
||||
S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime);
|
||||
break;
|
||||
}
|
||||
|
||||
return 1 + ndelays;
|
||||
}
|
||||
|
||||
|
||||
// Check if the instruction would conflict with instructions already
|
||||
// chosen for the current cycle
|
||||
//
|
||||
static inline bool
|
||||
ConflictsWithChoices(const SchedulingManager& S,
|
||||
MachineOpCode opCode)
|
||||
{
|
||||
// Check if the instruction must issue by itself, and some feasible
|
||||
// choices have already been made for this cycle
|
||||
if (S.getNumChoices() > 0 && S.schedInfo.isSingleIssue(opCode))
|
||||
return true;
|
||||
|
||||
// For each class that opCode belongs to, check if there are too many
|
||||
// instructions of that class.
|
||||
//
|
||||
const InstrSchedClass sc = S.schedInfo.getSchedClass(opCode);
|
||||
return (S.getNumChoicesInClass(sc) == S.schedInfo.getMaxIssueForClass(sc));
|
||||
}
|
||||
|
||||
|
||||
//************************* External Functions *****************************/
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Function: ViolatesMinimumGap
|
||||
//
|
||||
// Purpose:
|
||||
// Check minimum gap requirements relative to instructions scheduled in
|
||||
// previous cycles.
|
||||
// Note that we do not need to consider `nextEarliestIssueTime' here because
|
||||
// that is also captured in the earliest start times for each opcode.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
static inline bool
|
||||
ViolatesMinimumGap(const SchedulingManager& S,
|
||||
MachineOpCode opCode,
|
||||
const cycles_t inCycle)
|
||||
{
|
||||
return (inCycle < S.getEarliestStartTimeForOp(opCode));
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Function: instrIsFeasible
|
||||
//
|
||||
// Purpose:
|
||||
// Check if any issue restrictions would prevent the instruction from
|
||||
// being issued in the current cycle
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
bool
|
||||
instrIsFeasible(const SchedulingManager& S,
|
||||
MachineOpCode opCode)
|
||||
{
|
||||
// skip the instruction if it cannot be issued due to issue restrictions
|
||||
// caused by previously issued instructions
|
||||
if (ViolatesMinimumGap(S, opCode, S.getTime()))
|
||||
return false;
|
||||
|
||||
// skip the instruction if it cannot be issued due to issue restrictions
|
||||
// caused by previously chosen instructions for the current cycle
|
||||
if (ConflictsWithChoices(S, opCode))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Function: ScheduleInstructionsWithSSA
|
||||
//
|
||||
// Purpose:
|
||||
// Entry point for instruction scheduling on SSA form.
|
||||
// Schedules the machine instructions generated by instruction selection.
|
||||
// Assumes that register allocation has not been done, i.e., operands
|
||||
// are still in SSA form.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
bool
|
||||
ScheduleInstructionsWithSSA(Method* method,
|
||||
const TargetMachine &target)
|
||||
{
|
||||
SchedGraphSet graphSet(method, target);
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
|
||||
{
|
||||
cout << endl << "*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING"
|
||||
<< endl;
|
||||
graphSet.dump();
|
||||
}
|
||||
|
||||
for (SchedGraphSet::const_iterator GI=graphSet.begin();
|
||||
GI != graphSet.end(); ++GI)
|
||||
{
|
||||
SchedGraph* graph = (*GI).second;
|
||||
const vector<const BasicBlock*>& bbvec = graph->getBasicBlocks();
|
||||
assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
|
||||
const BasicBlock* bb = bbvec[0];
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintSchedTrace)
|
||||
cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
|
||||
|
||||
SchedPriorities schedPrio(method, graph); // expensive!
|
||||
SchedulingManager S(target, graph, schedPrio);
|
||||
|
||||
ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
|
||||
|
||||
ForwardListSchedule(S); // computes schedule in S
|
||||
|
||||
RecordSchedule((*GI).first, S); // records schedule in BB
|
||||
}
|
||||
|
||||
if (SchedDebugLevel >= Sched_PrintMachineCode)
|
||||
{
|
||||
cout << endl
|
||||
<< "*** Machine instructions after INSTRUCTION SCHEDULING" << endl;
|
||||
PrintMachineInstructions(method);
|
||||
}
|
||||
|
||||
return false; // no reason to fail yet
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user